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Message-ID: <f5ae0d20-3282-4386-b5dd-aa55142d2b7c@kernel.org>
Date: Tue, 21 Oct 2025 09:04:10 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Qiang Yu <qiang.yu@....qualcomm.com>, Vinod Koul <vkoul@...nel.org>,
 Kishon Vijay Abraham I <kishon@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Lorenzo Pieralisi <lpieralisi@...nel.org>,
 Krzysztof WilczyƄski <kwilczynski@...nel.org>,
 Manivannan Sadhasivam <mani@...nel.org>, Bjorn Helgaas
 <bhelgaas@...gle.com>, Bjorn Andersson <andersson@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-pci@...r.kernel.org, Qiang Yu <quic_qianyu@...cinc.com>
Subject: Re: [PATCH v5 2/6] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy:
 Document the Glymur QMP PCIe Gen4 2-lane PHY

On 18/10/2025 03:33, Qiang Yu wrote:
> From: Qiang Yu <quic_qianyu@...cinc.com>
> 
> The 4th and 6th PCIe instances on Glymur have Gen4 2-lane PHY. Document it
> as a separate compatible.
NAK,

Why are you duplicating Abel's patches?

Best regards,
Krzysztof

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