linux-kernel - Re: [PATCH v2 1/1] MIPS: Malta: Use pcibios_align

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <9ff182b0-076b-78fd-adec-99ae7ea5341f@linux.intel.com>
Date: Tue, 21 Oct 2025 15:51:09 +0300 (EEST)
From: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
To: "Maciej W. Rozycki" <macro@...am.me.uk>
cc: Bjorn Helgaas <helgaas@...nel.org>, 
    Thomas Bogendoerfer <tsbogend@...ha.franken.de>, linux-pci@...r.kernel.org, 
    Guenter Roeck <linux@...ck-us.net>, Bjorn Helgaas <bhelgaas@...gle.com>, 
    linux-mips@...r.kernel.org, LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 1/1] MIPS: Malta: Use pcibios_align_resource() to
 block io range

On Tue, 21 Oct 2025, Maciej W. Rozycki wrote:

> On Mon, 20 Oct 2025, Bjorn Helgaas wrote:
> 
> > > Since ae81aad5c2e1 ("MIPS: PCI: Use pci_enable_resources()") came
> > > through the PCI tree, I'd be happy to merge this as well, given your
> > > ack, Thomas.  It would be ideal to have a tested-by from Guenter.
> > > 
> > > I provisionally put it on pci/for-linus to facilitate testing.  If it
> > > doesn't solve the problem or you'd rather take it, Thomas, I'll be
> > > glad to drop it.
> > 
> > Added:
> > 
> >   Tested-by: Guenter Roeck <linux@...ck-us.net>
> >   Tested-by: Maciej W. Rozycki <macro@...am.me.uk>
> >   Acked-by: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
> > 
> > and dropped the Fixes: aa0980b80908 ("Fixes for system controllers for
> > Atlas/Malta core cards.")
> > 
> > If the missing resource reservations (dma1, tiger, dma page reg)
> > mentioned by Maciej are an issue or can be fixed up, let me know and
> > we can amend this.
> 
>  NB this comes from `plat_mem_setup' in arch/mips/mti-malta/malta-setup.c 
> iterating over `standard_io_resources'.  ISTR now this being my original 
> reason to come up with the approach taken with commit aa0980b80908 rather 
> than using PCIBIOS_MIN_IO.  Since the ranges are now owned by the PCI host 
> bridge, calls to `request_resource' referring `ioport_resource' fail.

So this platform would actually need multiple root bus IO resources to 
cover PIIX4 range without capturing non-PCI ranges?

>  I'm not sure offhand how to get a hold on the right handle under the new 
> arrangement in this platform code, but clearly it must be doable as x86 
> gets it right (and conversely Alpha gets it totally wrong).
> 
>  Also I think we should reserve the PCI port I/O window in the MMIO space 
> as well; something that I pondered back those 20 years ago already.  For 
> the system I've used here that'd show up as:
> 
> 10000000-1affffff : MSC PCI MEM
>   10000000-100fffff : 0000:00:0b.0
>   [...]
>   10142080-1014209f : 0000:00:0b.0
> 1b000000-1bffffff : MSC PCI I/O
> 1e000000-1e3fffff : 1e000000.flash flash@...00000
> 
> Most non-x86 PCI host bridges have one, but I haven't come across a Linux
> platform that would report it.
> 
>   Maciej
> 

-- 
 i.