linux-kernel - [PATCH 5/8] arm64: dts: imx8: add default clock rate for usdhc

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Message-Id: <20251022-dxl_dts-v1-5-8159dfdef8c5@nxp.com>
Date: Wed, 22 Oct 2025 12:50:25 -0400
From: Frank Li <Frank.Li@....com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>, 
 Sascha Hauer <s.hauer@...gutronix.de>, 
 Pengutronix Kernel Team <kernel@...gutronix.de>, 
 Fabio Estevam <festevam@...il.com>, Shenwei Wang <shenwei.wang@....com>, 
 Richard Cochran <richardcochran@...il.com>
Cc: devicetree@...r.kernel.org, imx@...ts.linux.dev, 
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, 
 netdev@...r.kernel.org, Frank Li <Frank.Li@....com>
Subject: [PATCH 5/8] arm64: dts: imx8: add default clock rate for usdhc

From: Shenwei Wang <shenwei.wang@....com>

Add default clock rate for usdhc nodes to support higher transfer speed.

Signed-off-by: Shenwei Wang <shenwei.wang@....com>
Signed-off-by: Frank Li <Frank.Li@....com>
---
 arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index ce6ef160fd5506cf6430be321ca75cb658669335..0b8b32f6976813515bc8d9dce5486074d0ec8b7e 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -77,6 +77,8 @@ usdhc1: mmc@...10000 {
 			 <&sdhc0_lpcg IMX_LPCG_CLK_5>,
 			 <&sdhc0_lpcg IMX_LPCG_CLK_0>;
 		clock-names = "ipg", "ahb", "per";
+		assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <400000000>;
 		power-domains = <&pd IMX_SC_R_SDHC_0>;
 		status = "disabled";
 	};
@@ -88,6 +90,8 @@ usdhc2: mmc@...20000 {
 			 <&sdhc1_lpcg IMX_LPCG_CLK_5>,
 			 <&sdhc1_lpcg IMX_LPCG_CLK_0>;
 		clock-names = "ipg", "ahb", "per";
+		assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <200000000>;
 		power-domains = <&pd IMX_SC_R_SDHC_1>;
 		fsl,tuning-start-tap = <20>;
 		fsl,tuning-step = <2>;
@@ -101,6 +105,8 @@ usdhc3: mmc@...30000 {
 			 <&sdhc2_lpcg IMX_LPCG_CLK_5>,
 			 <&sdhc2_lpcg IMX_LPCG_CLK_0>;
 		clock-names = "ipg", "ahb", "per";
+		assigned-clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <200000000>;
 		power-domains = <&pd IMX_SC_R_SDHC_2>;
 		status = "disabled";
 	};

-- 
2.34.1