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Message-ID: <f9aaa47e-4fa5-4b13-8abc-392d2c96512e@rock-chips.com> Date: Wed, 22 Oct 2025 11:44:34 +0800 From: zhangqing <zhangqing@...k-chips.com> To: Heiko Stuebner <heiko@...ech.de>, mturquette@...libre.com, sboyd@...nel.org, sugar.zhang@...k-chips.com, robh@...nel.org, krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-clk@...r.kernel.org, linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org, huangtao@...k-chips.com, finley.xiao@...k-chips.com Subject: Re: [PATCH v4 5/7] clk: rockchip: add support for pvtpll clk 在 2025/10/21 21:47, Heiko Stuebner 写道: > Am Dienstag, 21. Oktober 2025, 08:52:30 Mitteleuropäische Sommerzeit schrieb Elaine Zhang: >> Support to adjust pvtpll by volt-sel and otp. >> Support calibrate pvtpll init frequency. >> >> PVTPLL is used to monitor the chip performance variance caused by chip >> process, voltage and temperature, and generate a set of reference signals >> for adjusting the voltage of the chip. >> >> PVTPLL supports the following features: >> >> 1. A clock oscillation ring is integrated and used to generate a clock >> like signal (osc_clk),the frequency of this clock is determined >> by the cell delay value of clock oscillation ring circuit >> >> 2. A frequency counter(osc_cnt) is used to measure the frequency of osc_clk. >> >> 3. A externally input clock (ref_clk) is used as a reference clock for >> detecting the frequency of osc_clk. >> >> 4. A calculation counter uses ref_clk to generate a configurable >> periodic timing window. >> >> 5. Two clock counters are used to measure the frequency of the clock >> generated by OSC_WRAPPER? >> >> 6. Support for dividing the ref_clk and osc_clk >> >> 7. Support for configuring the effective polarity of the voltage >> regulator signal 'OUT' >> >> The clock path of cpu used pvtpll: >> >> --gpll--|--\ >> | \ | \ >> | \ | \ >> | \ | \ >> --v0pll--| mux |--[gate]--[div]--clk_core_src--|mux |--clk_core >> | / | / >> | / --ref_clk--[div]-cpu_pvtpll--| / >> --v1pll--| / | / >> |--/ >> >> Signed-off-by: Elaine Zhang <zhangqing@...k-chips.com> > [...] > >> + pvtpll->regmap_cru = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,cru"); > Not convinced about that :-) . > > (1) the cru itself already ioremaps the CRU memory, so having a syscon > there would ioremap that memory a second time. > (2) we should definitly not expose the whole CRU io-memory to other > drivers to write "random" stuff to. This will just invited further > hacks, where people want to take shortcuts with clock settings. > > Also this seems highly specific to the rv1126b. > > Looking at the registers, this is a clk-mux between that deepslow clock > and the actual pvtpll output and the config function really only > reparents to the pvtpll in all cases. > > So I believe this should in the worst case just be mux clock, but also > I see that the "correct" setting will already be set by the > > /* pvtpll src init */ > writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_CORECLKSEL_CON(0)); > writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_NPUCLKSEL_CON(0)); > writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VICLKSEL_CON(0)); > writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VEPUCLKSEL_CON(0)); > writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VCPCLKSEL_CON(0)); > > in the rv1126b clock driver? This configuration is only used to select the source clock of pvtpll, whether it is 24M or 32K. For pvtpll to function properly, it needs to be switched from the default 32K to 24M. > > So that whole mode setting should not be necessary at all maybe? Pvtpll adjusts the ring and len parameters according to the voltage and frequency, and calibrates and adjusts the parameter table of pvtpll based on the batch of chips. Pvtpll is located in pd. After the pd on/off, configuration information will be lost and some recovery operations need to be performed, so the address of cru is required. About the syscon attribute is used by the cpu dev freq driver to obtain pvtpll information.This depends on cpu dev freq driver. Upstream can remove the syscon next version. > > Thanks > Heiko > > > -- 张晴 瑞芯微电子股份有限公司 Rockchip Electronics Co.,Ltd 地址：福建省福州市铜盘路软件大道89号软件园A区21号楼 Add:No.21 Building, A District, No.89 Software Boulevard Fuzhou, Fujian 350003, P.R.China Tel:+86-0591-83991906-8601 邮编：350003 E-mail:elaine.zhang@...k-chips.com **************************************************************************** 保密提示：本邮件及其附件含有机密信息，仅发送给本邮件所指特定收件人。若非该特定收件人，请勿复制、使用或披露本邮件的任何内容。若误收本邮件，请从系统中永久性删除本邮件及所有附件，并以回复邮件或其他方式即刻告知发件人。福州瑞芯微电子有限公司拥有本邮件信息的著作权及解释权，禁止任何未经授权许可的侵权行为。 IMPORTANT NOTICE: This email is from Fuzhou Rockchip Electronics Co., Ltd .The contents of this email and any attachments may contain information that is privileged, confidential and/or exempt from disclosure under applicable law and relevant NDA. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information is STRICTLY PROHIBITED. Please immediately contact the sender as soon as possible and destroy the material in its entirety in any format. Thank you. ****************************************************************************
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