[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <20251022065507.1152071-1-ryan_chen@aspeedtech.com>
Date: Wed, 22 Oct 2025 14:55:04 +0800
From: Ryan Chen <ryan_chen@...eedtech.com>
To: ryan_chen <ryan_chen@...eedtech.com>, Thomas Gleixner
<tglx@...utronix.de>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
<krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Joel Stanley
<joel@....id.au>, Andrew Jeffery <andrew@...econstruct.com.au>,
<jk@...econstruct.com.au>, Kevin Chen <kevin_chen@...eedtech.com>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-aspeed@...ts.ozlabs.org>
Subject: [PATCH v5 0/3] AST2700 interrupt controller hierarchy support
This series introduces YAML bindings and driver support for the
ASPEED AST2700 interrupt controller hierarchy. The AST2700 SoC
contains two top-level interrupt controller blocks, INTC0 and
INTC1, each responsible for routing different interrupt groups
to various CPU targets.
v5:
- Adds two new YAML bindings:
- aspeed,ast2700-intc0.yaml
- aspeed,ast2700-intc1.yaml
- irq-aspeed-intc.c
- add aspeed,ast2700-intc0-ic, aspeed,ast2700-intc0-ic compatible.
v4:
- aspeed,ast2700-intc.yaml
- Clarify the relationship between INTC0/INTC1 parent nodes, the
aspeed,ast2700-intc-ic child nodes, and the GIC.
- Add a block diagram and DT examples showing the cascaded wiring
(GIC <- INTC0 <- INTC1 children).
- Mirrors the datasheet-described topology and register map, including
the separation of INTC0/INTC1 regions.
- Lets DT unambiguously express first-level (GIC parent) and cascaded
second-level (INTC0 parent) interrupt controllers via examples that
use `interrupts` for INTC0 children and `interrupts-extended` for
INTC1 children routed into INTC0.
- irq-ast2700-intc.c
- Drop all string decoding and human readable tables.
Debugfs now dumps raw routing/protection registers only.
- Split into a separate source file and made it modular
- If the compatible not match ast2700-intc0/1, bail out return -ENODEV.
v3:
- aspeed,ast2700-intc.yaml
- Clarify the relationship between INTC0/INTC1 parent nodes, the
aspeed,ast2700-intc-ic child nodes, and the GIC.
- Add a block diagram and DT examples showing the cascaded wiring
(GIC <- INTC0 <- INTC1 children).
- Mirrors the datasheet-described topology and register map, including
the separation of INTC0/INTC1 regions and their routing/protection
registers.
- Lets DT unambiguously express first-level (GIC parent) and cascaded
second-level (INTC0 parent) interrupt controllers via examples that
use `interrupts` for INTC0 children and `interrupts-extended` for
INTC1 children routed into INTC0.
- irq-aspeed-intc.c
- separate c file from irq-aspeed-intc.c
- make m
v2:
- fix dt bindingcheck
Ryan Chen (3):
dt-bindings: interrupt-controller: aspeed,ast2700: Add support for
INTC hierarchy
Irqchip/ast2700-intc: add debugfs support for routing/protection
display
irqchip: aspeed: add compatible strings for ast2700-intc0-ic and
ast2700-intc1-ic
.../aspeed,ast2700-intc0.yaml | 97 ++++++++++
.../aspeed,ast2700-intc1.yaml | 94 ++++++++++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-aspeed-intc.c | 2 +
drivers/irqchip/irq-ast2700-intc.c | 174 ++++++++++++++++++
6 files changed, 374 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc0.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc1.yaml
create mode 100644 drivers/irqchip/irq-ast2700-intc.c
--
2.34.1
Powered by blists - more mailing lists