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Message-Id: <20251022-optimize_pll_driver-v1-0-a275722fb6f4@amlogic.com>
Date: Wed, 22 Oct 2025 14:58:50 +0800
From: Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@...nel.org>
To: Neil Armstrong <neil.armstrong@...aro.org>,
Jerome Brunet <jbrunet@...libre.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Kevin Hilman <khilman@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc: linux-amlogic@...ts.infradead.org, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Chuan Liu <chuan.liu@...ogic.com>
Subject: [PATCH 0/3] clk: amlogic: optimize the PLL driver
This patch series consists of three topics involving the amlogic PLL
driver:
- Fix out-of-range PLL frequency setting
- Optimize PLL enable timing
- Correct l_detect bit control
For easier review and management, these are submitted as a single
patch series.
Signed-off-by: Chuan Liu <chuan.liu@...ogic.com>
---
Chuan Liu (3):
clk: amlogic: Fix out-of-range PLL frequency setting
clk: amlogic: Optimize PLL enable timing
clk: amlogic: Correct l_detect bit control
drivers/clk/meson/a1-pll.c | 1 +
drivers/clk/meson/clk-pll.c | 76 ++++++++++++++++++++++++++++-----------------
drivers/clk/meson/clk-pll.h | 2 ++
3 files changed, 51 insertions(+), 28 deletions(-)
---
base-commit: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf
change-id: 20251020-optimize_pll_driver-7bef91876c41
Best regards,
--
Chuan Liu <chuan.liu@...ogic.com>
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