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Message-Id: <20251022074710.575-3-nas.chung@chipsnmedia.com>
Date: Wed, 22 Oct 2025 16:47:03 +0900
From: Nas Chung <nas.chung@...psnmedia.com>
To: mchehab@...nel.org,
hverkuil@...all.nl,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
shawnguo@...nel.org,
s.hauer@...gutronix.de
Cc: linux-media@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-imx@....com,
linux-arm-kernel@...ts.infradead.org,
jackson.lee@...psnmedia.com,
lafley.kim@...psnmedia.com,
marek.vasut@...lbox.org,
Nas Chung <nas.chung@...psnmedia.com>
Subject: [PATCH v4 2/9] dt-bindings: media: nxp: Add Wave6 video codec device
Add documentation for the Chips&Media Wave6 video codec on
NXP i.MX SoCs.
The Wave6 video codec functionality is split between a VPU
control region and VPU core regions.
The VPU control region is represented as the parent node and
manages shared resources such as firmware memory. Each VPU
core region is represented as a child node and provides the
actual encoding and decoding capabilities.
Both the control and core regions may be assigned IOMMU
stream IDs for DMA isolation.
Signed-off-by: Nas Chung <nas.chung@...psnmedia.com>
---
.../bindings/media/nxp,imx95-vpu.yaml | 162 ++++++++++++++++++
MAINTAINERS | 7 +
2 files changed, 169 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/nxp,imx95-vpu.yaml
diff --git a/Documentation/devicetree/bindings/media/nxp,imx95-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx95-vpu.yaml
new file mode 100644
index 000000000000..2ee8d22ba468
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/nxp,imx95-vpu.yaml
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/nxp,imx95-vpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Chips&Media Wave6 Series multi-standard codec IP on NXP i.MX SoCs
+
+maintainers:
+ - Nas Chung <nas.chung@...psnmedia.com>
+ - Jackson Lee <jackson.lee@...psnmedia.com>
+
+description:
+ The Chips&Media Wave6 codec IP is a multi-standard video encoder/decoder.
+ On NXP i.MX SoCs, Wave6 codec IP functionality is split between
+ the VPU control region and the VPU core region.
+ The VPU control region manages shared resources such as firmware memory,
+ while the VPU core region provides encoding and decoding
+ capabilities. The VPU core cannot operate independently without
+ the VPU control region.
+ Both the VPU control and core regions may be assigned IOMMU stream IDs for
+ DMA isolation.
+
+properties:
+ compatible:
+ enum:
+ - nxp,imx95-vpu
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ memory-region:
+ maxItems: 1
+
+ sram:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle of the SRAM memory region node.
+
+ "#cooling-cells":
+ const: 2
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ ranges: true
+
+patternProperties:
+ "^video-core@[0-9a-f]+$":
+ type: object
+ description:
+ A VPU core region within the Chips&Media Wave6 codec IP.
+ Each core provides encoding and decoding capabilities and operates
+ under the control of the VPU control region.
+ additionalProperties: false
+
+ properties:
+ compatible:
+ enum:
+ - nxp,imx95-vpu-core
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - clocks
+ - power-domains
+ - interrupts
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - power-domains
+ - memory-region
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/nxp,imx95-clock.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ video-codec@...c0000 {
+ compatible = "nxp,imx95-vpu";
+ reg = <0x0 0x4c4c0000 0x0 0x10000>;
+ clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_WAVE>;
+ power-domains = <&scmi_perf 10>;
+ iommus = <&smmu 0x32>;
+ memory-region = <&vpu_boot>;
+ sram = <&sram1>;
+ #cooling-cells = <2>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ video-core@...80000 {
+ compatible = "nxp,imx95-vpu-core";
+ reg = <0x0 0x4c480000 0x0 0x10000>;
+ clocks = <&scmi_clk 115>;
+ power-domains = <&scmi_devpd 21>;
+ iommus = <&smmu 0x33>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ video-core@...90000 {
+ compatible = "nxp,imx95-vpu-core";
+ reg = <0x0 0x4c490000 0x0 0x10000>;
+ clocks = <&scmi_clk 115>;
+ power-domains = <&scmi_devpd 21>;
+ iommus = <&smmu 0x34>;
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ video-core@...a0000 {
+ compatible = "nxp,imx95-vpu-core";
+ reg = <0x0 0x4c4a0000 0x0 0x10000>;
+ clocks = <&scmi_clk 115>;
+ power-domains = <&scmi_devpd 21>;
+ iommus = <&smmu 0x35>;
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ video-core@...b0000 {
+ compatible = "nxp,imx95-vpu-core";
+ reg = <0x0 0x4c4b0000 0x0 0x10000>;
+ clocks = <&scmi_clk 115>;
+ power-domains = <&scmi_devpd 21>;
+ iommus = <&smmu 0x36>;
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index f7351fced572..a57fee506d57 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -27558,6 +27558,13 @@ S: Maintained
F: Documentation/devicetree/bindings/media/cnm,wave521c.yaml
F: drivers/media/platform/chips-media/wave5/
+WAVE6 VPU CODEC DRIVER
+M: Nas Chung <nas.chung@...psnmedia.com>
+M: Jackson Lee <jackson.lee@...psnmedia.com>
+L: linux-media@...r.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/media/nxp,imx95-vpu.yaml
+
WHISKEYCOVE PMIC GPIO DRIVER
M: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@...ux.intel.com>
L: linux-gpio@...r.kernel.org
--
2.31.1
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