Message-ID: <b7c569b4-12c1-438b-971b-75c0f84c4837@kernel.org>
Date: Wed, 22 Oct 2025 06:22:48 -0500
From: Dinh Nguyen <dinguyen@...nel.org>
To: Lothar Rubusch <l.rubusch@...il.com>, robh@...nel.org,
 krzk+dt@...nel.org, conor+dt@...nel.org, martin.petersen@...cle.com,
 pabeni@...hat.com, rostedt@...dmis.org, bhelgaas@...gle.com
Cc: arnd@...db.de, matthew.gerlach@...era.com, tien.fong.chee@...era.com,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v7 00/11] Add Enclustra Arria10 and Cyclone5 SoMs



On 10/18/25 07:11, Lothar Rubusch wrote:
> This series was already presented in November 2024.
> https://lkml.org/lkml/2024/11/16/198
> 
> Due to the ongoing complex situation with Intel's maintainership,
> the series likely did not progress further at the time. In early
> 2025, Tien Fong Chee (in CC) informed me that Altera is expected
> to resume maintainership in late 2025. I was referred to Matthew
> Gerlach (also CC'd), who, as I understand, is taking over at least
> part of the Intel/Altera-related responsibilities.
> 
> At this year’s OSS in Amsterdam, I had an encouraging discussion
> with Arnd Bergmann (CC’d), which motivated me to continue pursuing
> this patch series.
> 
> Hence, a slightly reworded update goes now again to the mailing lists
> and will drive the binding check bot crazy. While not all Altera
> bindings may be fully resolved yet, this series should not introduce
> any new issues.
> I’m submitting it based on prior acknowledgments and will wait a few
> weeks to see if a maintainer responds. If it remains orphaned, I’ll
> follow up with you, Arnd, as previously mentioned - this is just a
> heads-up for now.
> 
> I hope this approach is acceptable. Please let me know otherwise.
> Thank you for all the support in this so far.
> 
> Add device-tree support for the following SoMs:
> - Mercury SA1 (cyclone5)
> - Mercury+ SA2 (cyclone5)
> - Mercury+ AA1 (arria10)
> 
> Further add device-tree support for the corresponding carrier boards:
> - Mercury+ PE1
> - Mercury+ PE3
> - Mercury+ ST1
> 
> Finally, provide generic support for combinations of the above with
> one of the boot-modes
> - SD
> - eMMC
> - QSPI
> 
> All of the above elements can be freely combined, with the combinations
> specified in the provided .dts files. This renders the existing .dts file
> unnecessary. Any additional minor fixes to the dtbs_checks are applied
> separately.
> 
> This approach is also necessary for integrating with the corresponding
> bootloader using dts/upstream, which is one of the reasons for the .dtsi
> split.
> 
> Note: I used AI tools to help refine the wording of the commit messages.
> 
> Signed-off-by: Lothar Rubusch <l.rubusch@...il.com>
> ---
> v6 -> v7:
> - dt-bindings: alphabetic order for aa1 variants fixed
> 
> v5 -> v6:
> - update to recent kernel version
> - add Arnd Bergman in CC (refered to OSS / Amsterdam)
> - add Matthew Gerlach in CC
> - add chee tien fong in CC
> - change phy-mode "rgmii" to "rgmii-id", due to binding checks, similar
>    boards in that context and the allowing internal delay (id) or strict
>    no internal delay, seems to make no difference here
> - removal of compatibility "spansion,s25fl512s" due to deprecation of
>    older vendor properties for "jedec,spi-nor"
> - change commit header wording "combinations" to "variants"
> 
> v4 -> v5:
> - separate generic socfpga dt fixes from this patch set. The focus of this
>    patch set is the dts/dtsi files and related bindings, not additional
>    intel/socfpga refactoring
> 
> v3 -> v4:
> - add separate patch to match "snps,dwmac" compatible in corresponding
>    driver, required by binding check
> - replace non-standard node names in .dtsi files by node names recommended
>    by the device tree standard v0.4
> 
> v2 -> v3:
> - dropped the patch to add the socfpga clock bindings:
>    Documentation/devicetree/bindings/clock/altr,socfpga-a10.yaml
>    reason: refactoring the "altr,socfpga-" TXT files to .yaml files is a
>    different story involving several other files, thus can be part of a
>    future patch series, not related to the current upstreaming the
>    Enclustra DTS support, so dropped
> - adjust comments on boot mode selection
> - adjust titles to several bindings patches
> 
> v1 -> v2:
> - split bindings and DT adjustments/additions
> - add several fixes to the socfpga.dtsi and socfpga_arria10.dtsi where
>    bindings did not match
> - extend existing bindings by properties and nods from arria10 setup
> - implement the clock binding altr,socfpga-a10.yaml based on existing
>    text file, rudimentary datasheet study and requirements of the
>    particular DT setup
> ---
> Lothar Rubusch (11):
>    ARM: dts: socfpga: add Enclustra boot-mode dtsi
>    ARM: dts: socfpga: add Enclustra base-board dtsi
>    ARM: dts: socfpga: add Enclustra Mercury SA1
>    dt-bindings: altera: add Enclustra Mercury SA1
>    ARM: dts: socfpga: add Enclustra Mercury+ SA2
>    dt-bindings: altera: add binding for Mercury+ SA2
>    ARM: dts: socfpga: add Mercury AA1 variants
>    dt-bindings: altera: add Mercury AA1 variants
>    ARM: dts: socfpga: removal of generic PE1 dts
>    dt-bindings: altera: removal of generic PE1 dts
>    ARM: dts: socfpga: add Enclustra SoM dts files
> 
>   .../devicetree/bindings/arm/altera.yaml       |  24 ++-
>   arch/arm/boot/dts/intel/socfpga/Makefile      |  25 ++-
>   .../socfpga/socfpga_arria10_mercury_aa1.dtsi  | 143 ++++++++++++++---
>   .../socfpga_arria10_mercury_aa1_pe1_emmc.dts  |  16 ++
>   .../socfpga_arria10_mercury_aa1_pe1_qspi.dts  |  16 ++
>   .../socfpga_arria10_mercury_aa1_pe1_sdmmc.dts |  16 ++
>   .../socfpga_arria10_mercury_aa1_pe3_emmc.dts  |  16 ++
>   .../socfpga_arria10_mercury_aa1_pe3_qspi.dts  |  16 ++
>   .../socfpga_arria10_mercury_aa1_pe3_sdmmc.dts |  16 ++
>   .../socfpga_arria10_mercury_aa1_st1_emmc.dts  |  16 ++
>   .../socfpga_arria10_mercury_aa1_st1_qspi.dts  |  16 ++
>   .../socfpga_arria10_mercury_aa1_st1_sdmmc.dts |  16 ++
>   .../socfpga/socfpga_arria10_mercury_pe1.dts   |  55 -------
>   .../socfpga/socfpga_cyclone5_mercury_sa1.dtsi | 143 +++++++++++++++++
>   .../socfpga_cyclone5_mercury_sa1_pe1_emmc.dts |  16 ++
>   .../socfpga_cyclone5_mercury_sa1_pe1_qspi.dts |  16 ++
>   ...socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts |  16 ++
>   .../socfpga_cyclone5_mercury_sa1_pe3_emmc.dts |  16 ++
>   .../socfpga_cyclone5_mercury_sa1_pe3_qspi.dts |  16 ++
>   ...socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts |  16 ++
>   .../socfpga_cyclone5_mercury_sa1_st1_emmc.dts |  16 ++
>   .../socfpga_cyclone5_mercury_sa1_st1_qspi.dts |  16 ++
>   ...socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts |  16 ++
>   .../socfpga/socfpga_cyclone5_mercury_sa2.dtsi | 146 ++++++++++++++++++
>   .../socfpga_cyclone5_mercury_sa2_pe1_qspi.dts |  16 ++
>   ...socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts |  16 ++
>   .../socfpga_cyclone5_mercury_sa2_pe3_qspi.dts |  16 ++
>   ...socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts |  16 ++
>   .../socfpga_cyclone5_mercury_sa2_st1_qspi.dts |  16 ++
>   ...socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts |  16 ++
>   ...cfpga_enclustra_mercury_bootmode_emmc.dtsi |  12 ++
>   ...cfpga_enclustra_mercury_bootmode_qspi.dtsi |   8 +
>   ...fpga_enclustra_mercury_bootmode_sdmmc.dtsi |   8 +
>   .../socfpga_enclustra_mercury_pe1.dtsi        |  33 ++++
>   .../socfpga_enclustra_mercury_pe3.dtsi        |  55 +++++++
>   .../socfpga_enclustra_mercury_st1.dtsi        |  15 ++
>   36 files changed, 972 insertions(+), 79 deletions(-)
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts
>   delete mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_emmc.dtsi
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qspi.dtsi
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi
> 
> 
> base-commit: 4b17a60d1e1c2d9d2ccbd58642f6f4ac2fa364ba


Applied!

Thanks,
Dinh

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