linux-kernel - Re: [RFC PATCH v2 08/18] iommu/riscv: Use MSI table to enable IMSIC access

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Message-Id: <20251023134708.1192-1-jinvas@126.com>
Date: Thu, 23 Oct 2025 21:47:08 +0800
From: Jinvas <jinvas@....com>
To: jgg@...dia.com
Cc: ajones@...tanamicro.com,
	alex.williamson@...hat.com,
	alex@...ti.fr,
	anup@...infault.org,
	atish.patra@...ux.dev,
	iommu@...ts.linux.dev,
	joro@...tes.org,
	kvm-riscv@...ts.infradead.org,
	kvm@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	palmer@...belt.com,
	paul.walmsley@...ive.com,
	robin.murphy@....com,
	tglx@...utronix.de,
	tjeznach@...osinc.com,
	will@...nel.org,
	zong.li@...ive.com
Subject: Re: [RFC PATCH v2 08/18] iommu/riscv: Use MSI table to enable IMSIC access

On Mon, 22 Sep 2025 20:56:51 -0300, Jason Gunthorpe wrote:
> We no longer need to support 32 bit builds and we missed this while
> cleaning up.
> Right now the only way to deal with this would be to only use one of
> the S1 or S2 and make that decision when the iommu driver starts. You
> can return the right SW_MSI/HW_MSI based on which PAGING domain style
> the driver is going to use.

> I recommend if the S2 is available you make the driver always use the
> S2 for everything and ignore the S1 except for explicit two stage
> translation setup by a hypervisor. Thus always return HW_MSI.
> If the iommu does not support S2 then always use S1 and always return
> SW_MSI.

I strongly agree with this suggestion,
because on one hand, the confusing design of RISC-V —
particularly the translation rules of the msix_table —
leads to different translation behaviors in S1 and S2 modes;

on the other hand,
designing a proper caching mechanism for the msix_table
in both S1 and S2 modes is quite challenging.

> Signed-off-by: Jason Gunthorpe <jgg@...dia.com>

Thanks for the patch!

Best regards,
jinvas