[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <20251023040224.1485946-1-quic_mmanikan@quicinc.com>
Date: Thu, 23 Oct 2025 09:32:24 +0530
From: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
To: <andersson@...nel.org>, <konradybcio@...nel.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>,
<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
CC: <quic_srichara@...cinc.com>, <quic_varada@...cinc.com>,
<kathiravan.thirumoorthy@....qualcomm.com>
Subject: [PATCH v1] arm64: dts: qcom: ipq5424: add gpio regulator for cpu power supply
Add a GPIO-controlled regulator node for the CPU rail on the
IPQ5424 RDP466 platform. This regulator supports two voltage
levels 850mV and 1000mV.
Update CPU nodes to reference the regulator via the `cpu-supply`
property, and add the required pinctrl configuration for GPIO17.
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
---
arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 24 +++++++++++++++++++++
arch/arm64/boot/dts/qcom/ipq5424.dtsi | 4 ++++
2 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
index 738618551203..6d14eb2fe821 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
@@ -46,6 +46,23 @@ led-0 {
};
};
+ vreg_apc: regulator-vreg-apc {
+ compatible = "regulator-gpio";
+ regulator-name = "vreg_apc";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <250>;
+
+ gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <850000 0>, <1000000 1>;
+
+ pinctrl-0 = <®ulator_gpio_default>;
+ pinctrl-names = "default";
+ };
+
vreg_misc_3p3: regulator-usb-3p3 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
@@ -171,6 +188,13 @@ gpio_leds_default: gpio-leds-default-state {
bias-pull-down;
};
+ regulator_gpio_default: regulator-gpio-default-state {
+ pins = "gpio17";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
spi0_default_state: spi0-default-state {
clk-pins {
pins = "gpio6";
diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index ef2b52f3597d..70702c80c626 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -56,6 +56,7 @@ cpu0: cpu@0 {
clocks = <&apss_clk APSS_SILVER_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&vreg_apc>;
interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
l2_0: l2-cache {
@@ -81,6 +82,7 @@ cpu1: cpu@100 {
clocks = <&apss_clk APSS_SILVER_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&vreg_apc>;
interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
l2_100: l2-cache {
@@ -100,6 +102,7 @@ cpu2: cpu@200 {
clocks = <&apss_clk APSS_SILVER_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&vreg_apc>;
interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
l2_200: l2-cache {
@@ -119,6 +122,7 @@ cpu3: cpu@300 {
clocks = <&apss_clk APSS_SILVER_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&vreg_apc>;
interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
l2_300: l2-cache {
base-commit: fe45352cd106ae41b5ad3f0066c2e54dbb2dfd70
--
2.34.1
Powered by blists - more mailing lists