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Message-ID: <87zf9hwh5j.ffs@tglx>
Date: Thu, 23 Oct 2025 21:29:44 +0200
From: Thomas Gleixner <tglx@...utronix.de>
To: Lucas Zampieri <lzampier@...hat.com>, linux-kernel@...r.kernel.org
Cc: Lucas Zampieri <lzampier@...hat.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>, Samuel
Holland <samuel.holland@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>, Vivian
Wang <dramforever@...e.com>, Charles Mirabile <cmirabil@...hat.com>,
devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v6 0/4] Add UltraRISC DP1000 PLIC support
On Thu, Oct 23 2025 at 15:00, Lucas Zampieri wrote:
> This series adds support for the PLIC implementation in the UltraRISC
> DP1000 SoC. The UR-CP100 cores used in the DP1000 have a hardware bug in
> their PLIC claim register where reading it while multiple interrupts are
> pending can return the wrong interrupt ID. The workaround temporarily
> disables all interrupts except the first pending one before reading the
> claim register, then restores the previous state.
>
> The driver matches on "ultrarisc,cp100-plic" (CPU core compatible), allowing
> the quirk to apply to all SoCs using UR-CP100 cores (currently DP1000,
> potentially future SoCs).
>
> Charles Mirabile (3):
> dt-bindings: interrupt-controller: add UltraRISC DP1000 PLIC
> irqchip/plic: enable optimization of interrupt enable state
That one never showed up. Neither in my inbox nor on lore
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