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Message-Id: <20251023-mt8196-ufs-v3-3-0f04b4a795ff@collabora.com>
Date: Thu, 23 Oct 2025 21:49:21 +0200
From: Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
To: Alim Akhtar <alim.akhtar@...sung.com>,
Avri Altman <avri.altman@....com>, Bart Van Assche <bvanassche@....org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
Chunfeng Yun <chunfeng.yun@...iatek.com>, Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Peter Wang <peter.wang@...iatek.com>, Stanley Jhu <chu.stanley@...il.com>,
"James E.J. Bottomley" <James.Bottomley@...senPartnership.com>,
"Martin K. Petersen" <martin.petersen@...cle.com>,
Philipp Zabel <p.zabel@...gutronix.de>, Liam Girdwood <lgirdwood@...il.com>,
Mark Brown <broonie@...nel.org>
Cc: Louis-Alexis Eyraud <louisalexis.eyraud@...labora.com>,
kernel@...labora.com, linux-scsi@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org,
linux-phy@...ts.infradead.org,
Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
Subject: [PATCH v3 03/24] dt-bindings: ufs: mediatek,ufs: Add mt8196
variant
The MediaTek MT8196 SoC's UFS controller uses three additional clocks
compared to the MT8195, and a different set of supplies. It is therefore
not compatible with the MT8195.
While it does have a AVDD09_UFS_1 pin in addition to the AVDD09_UFS pin,
it appears that these two pins are commoned together, as the board
schematic I have access to uses the same supply for both, and the
downstream driver does not distinguish between the two supplies either.
The pin that vcc-supply goes to is unknown; this is because the only
schematic I have access to is incomplete in this regard. However, from
experiments, I do know that the vemc supply must be turned on for UFS to
work.
Add a compatible for it, and modify the binding correspondingly.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
---
.../devicetree/bindings/ufs/mediatek,ufs.yaml | 83 +++++++++++++++++++++-
1 file changed, 82 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
index 364672bc65b1..57c944fd0318 100644
--- a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
@@ -15,10 +15,11 @@ properties:
- mediatek,mt8183-ufshci
- mediatek,mt8192-ufshci
- mediatek,mt8195-ufshci
+ - mediatek,mt8196-ufshci
clocks:
minItems: 1
- maxItems: 13
+ maxItems: 16
clock-names:
minItems: 1
@@ -36,6 +37,9 @@ properties:
- const: crypt_perf
- const: ufs_rx_symbol0
- const: ufs_rx_symbol1
+ - const: ufs_sel
+ - const: ufs_sel_min_src
+ - const: ufs_sel_max_src
operating-points-v2: true
@@ -127,9 +131,28 @@ allOf:
properties:
clocks:
minItems: 13
+ maxItems: 13
clock-names:
minItems: 13
+ maxItems: 13
avdd09-supply: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8196-ufshci
+ then:
+ properties:
+ clocks:
+ minItems: 16
+ maxItems: 16
+ clock-names:
+ minItems: 16
+ maxItems: 16
+ vcc-supply:
+ description: Must point to a "vemc" supply, unknown which pin it feeds
+ required:
+ - operating-points-v2
examples:
- |
@@ -178,3 +201,61 @@ examples:
vccq2-supply = <&mt6359_vbbck_ldo_reg>;
mediatek,ufs-disable-mcq;
};
+ - |
+ #include <dt-bindings/reset/mediatek,mt8196-resets.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ ufshci@...10000 {
+ compatible = "mediatek,mt8196-ufshci";
+ reg = <0x16810000 0x2a00>;
+ interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&ufs_ao_clk 6>,
+ <&ufs_ao_clk 7>,
+ <&clk26m>,
+ <&ufs_ao_clk 3>,
+ <&clk26m>,
+ <&ufs_ao_clk 4>,
+ <&ufs_ao_clk 0>,
+ <&topckgen 7>,
+ <&topckgen 41>,
+ <&topckgen 105>,
+ <&topckgen 83>,
+ <&ufs_ao_clk 1>,
+ <&ufs_ao_clk 2>,
+ <&topckgen 42>,
+ <&topckgen 84>,
+ <&topckgen 102>;
+ clock-names = "ufs",
+ "ufs_aes",
+ "ufs_tick",
+ "unipro_sysclk",
+ "unipro_tick",
+ "unipro_mp_bclk",
+ "ufs_tx_symbol",
+ "ufs_mem_sub",
+ "crypt_mux",
+ "crypt_lp",
+ "crypt_perf",
+ "ufs_rx_symbol0",
+ "ufs_rx_symbol1",
+ "ufs_sel",
+ "ufs_sel_min_src",
+ "ufs_sel_max_src";
+
+ operating-points-v2 = <&ufs_opp_table>;
+
+ phys = <&ufsphy>;
+
+ avdd09-supply = <&mt6363_vsram_modem>;
+ vcc-supply = <&mt6363_vemc>;
+ vcc-supply-1p8;
+ vccq-supply = <&mt6363_va12_2>;
+ vccq2-supply = <&mt6363_vufs12>;
+
+ resets = <&ufs_ao_clk MT8196_UFSAO_RST1_UFS_UNIPRO>,
+ <&ufs_ao_clk MT8196_UFSAO_RST1_UFS_CRYPTO>,
+ <&ufs_ao_clk MT8196_UFSAO_RST1_UFSHCI>;
+ reset-names = "unipro", "crypto", "hci";
+ mediatek,ufs-disable-mcq;
+ };
--
2.51.1.dirty
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