linux-kernel - Re: [PATCH v6 4/5] PCI/ERR: Use pcie_aer_is_native() to check for native AER control

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Message-ID: <aPoDbKebJD30NjKG@wunner.de>
Date: Thu, 23 Oct 2025 12:29:00 +0200
From: Lukas Wunner <lukas@...ner.de>
To: Shuai Xue <xueshuai@...ux.alibaba.com>
Cc: linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
	linuxppc-dev@...ts.ozlabs.org, bhelgaas@...gle.com,
	kbusch@...nel.org, sathyanarayanan.kuppuswamy@...ux.intel.com,
	mahesh@...ux.ibm.com, oohall@...il.com, Jonathan.Cameron@...wei.com,
	terry.bowman@....com, tianruidong@...ux.alibaba.com
Subject: Re: [PATCH v6 4/5] PCI/ERR: Use pcie_aer_is_native() to check for
 native AER control

On Mon, Oct 20, 2025 at 10:45:31PM +0800, Shuai Xue wrote:
> 	if (host->native_aer || pcie_ports_native) {
> 		pcie_clear_device_status(bridge);
> 		pci_aer_clear_nonfatal_status(bridge);
> 	}
> 
> This code clears both the PCIe Device Status register and AER status
> registers when in native AER mode.
> 
> pcie_clear_device_status() is renamed from
> pci_aer_clear_device_status(). Does it intends to clear only AER error
> status?
> 
> - BIT 0: Correctable Error Detected
> - BIT 1: Non-Fatal Error Detected
> - BIT 2: Fatal Error Detected
> - BIT 3: Unsupported Request Detected
> 
> From PCIe spec, BIT 0-2 are logged for functions supporting Advanced
> Error Handling.
> 
> I am not sure if we should clear BIT 3, and also BIT 6 (Emergency Power
> Reduction Detected) and in case a AER error.

AFAIUI, bits 0 to 3 are what the PCIe r7.0 sec 6.2.1 calls
"baseline capability" error reporting.  They're supported
even if AER is not supported.

Bit 6 has nothing to do with this AFAICS.

Thanks,

Lukas