linux-kernel - Re: issue with [PATCH v6 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk

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Message-Id: <20251023110922.186619-1-laura.nao@collabora.com>
Date: Thu, 23 Oct 2025 13:09:22 +0200
From: Laura Nao <laura.nao@...labora.com>
To: frank-w@...lic-files.de
Cc: angelogioacchino.delregno@...labora.com,
	conor+dt@...nel.org,
	daniel@...rotopia.org,
	devicetree@...r.kernel.org,
	guangjie.song@...iatek.com,
	kernel@...labora.com,
	krzk+dt@...nel.org,
	laura.nao@...labora.com,
	linux-arm-kernel@...ts.infradead.org,
	linux-clk@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-mediatek@...ts.infradead.org,
	matthias.bgg@...il.com,
	mturquette@...libre.com,
	netdev@...r.kernel.org,
	p.zabel@...gutronix.de,
	richardcochran@...il.com,
	robh@...nel.org,
	sboyd@...nel.org,
	wenst@...omium.org
Subject: Re: issue with [PATCH v6 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct

Hi Frank,

On 10/12/25 19:50, Frank Wunderlich wrote:
> Hi,
>
> this patch seems to break at least the mt7987 device i'm currently working on with torvalds/master + a bunch of some patches for mt7987 support.
>
> if i revert these 2 commits my board works again:
>
> Revert "clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct" => 8ceff24a754a
> Revert "clk: mediatek: clk-gate: Add ops for gates with HW voter"
>
> if i reapply the first one (i had to revert the second before), it is broken again.
>
> I have seen no changes to other clock drivers in mtk-folder. Mt7987 clk driver is not upstream yet, maybe you can help us changing this driver to work again.
>
> this is "my" commit adding the mt7987 clock driver...
>
> https://github.com/frank-w/BPI-Router-Linux/commit/7480615e752dee7ea9e60dfaf31f39580b4bf191
>
> start of trace (had it sometimes with mmc or spi and a bit different with 2p5g phy, but this is maybe different issue):
>
> [    5.593308] Unable to handle kernel paging request at virtual address ffffffc081371f88
> [    5.593322] Mem abort info:
> [    5.593324]   ESR = 0x0000000096000007
> [    5.593326]   EC = 0x25: DABT (current EL), IL = 32 bits
> [    5.593329]   SET = 0, FnV = 0
> [    5.593331]   EA = 0, S1PTW = 0
> [    5.593333]   FSC = 0x07: level 3 translation fault
> [    5.593336] Data abort info:
> [    5.593337]   ISV = 0, ISS = 0x00000007, ISS2 = 0x00000000
> [    5.593340]   CM = 0, WnR = 0, TnD = 0, TagAccess = 0
> [    5.593343]   GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
> [    5.593345] swapper pgtable: 4k pages, 39-bit VAs, pgdp=0000000045294000
> [    5.593349] [ffffffc081371f88] pgd=1000000045a7f003, p4d=1000000045a7f003, pud=1000000045a7f003, pmd=1000000045a82003, pte=0000000000000000
> [    5.593364] Internal error: Oops: 0000000096000007 [#1]  SMP
> [    5.593369] Modules linked in:
> [    5.593375] CPU: 0 UID: 0 PID: 1570 Comm: udevd Not tainted 6.17.0-bpi-r4 #7 NONE 
> [    5.593381] Hardware name: Bananapi BPI-R4-LITE (DT)
> [    5.593385] pstate: 204000c5 (nzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> [    5.593390] pc : mtk_cg_enable+0x14/0x38
> [    5.593404] lr : clk_core_enable+0x70/0x16c
> [    5.593411] sp : ffffffc085853090
> [    5.593413] x29: ffffffc085853090 x28: 0000000000000000 x27: ffffffc0800b82c4
> [    5.593420] x26: ffffffc085853754 x25: 0000000000000004 x24: ffffff80001828f4
> [    5.593426] x23: 0000000000000000 x22: ffffff80030620c0 x21: ffffff8007819580
> [    5.593432] x20: 0000000000000000 x19: ffffff8000feee00 x18: 0000003e39f23000
> [    5.593438] x17: ffffffffffffffff x16: 0000000000020000 x15: ffffff8002f590a0
> [    5.593444] x14: ffffff800346e000 x13: 0000000000000000 x12: 0000000000000000
> [    5.593450] x11: 0000000000000001 x10: 0000000000000000 x9 : 0000000000000000
> [    5.593455] x8 : ffffffc085853528 x7 : 0000000000000000 x6 : 0000000000002c01
> [    5.593461] x5 : ffffffc080858794 x4 : 0000000000000014 x3 : 0000000000000001
> [    5.593467] x2 : 0000000000000000 x1 : ffffffc081371f70 x0 : ffffff8001028c00
> [    5.593473] Call trace:
> [    5.593476]  mtk_cg_enable+0x14/0x38 (P)
> [    5.593484]  clk_core_enable+0x70/0x16c
> [    5.593490]  clk_enable+0x28/0x54
> [    5.593496]  mtk_spi_runtime_resume+0x84/0x174
> [    5.593506]  pm_generic_runtime_resume+0x2c/0x44
> [    5.593513]  __rpm_callback+0x40/0x228
> [    5.593521]  rpm_callback+0x38/0x80
> [    5.593527]  rpm_resume+0x590/0x774
> [    5.593533]  __pm_runtime_resume+0x5c/0xcc
> [    5.593539]  spi_mem_access_start.isra.0+0x38/0xdc
> [    5.593545]  spi_mem_exec_op+0x40c/0x4e0
>
> it is not clear for me, how to debug further as i have different clock drivers (but i guess either the infracfg is the right).
> maybe the critical-flag is not passed?
>
> regards Frank
>

Could you try adding some debug prints to help identify the specific 
gate/gates causing the issue? It would be very helpful in narrowing 
down the problem.

A couple notes - I noticed that some mux-gate clocks have -1 assigned to 
the _gate, _upd_ofs, and _upd unsigned int fields. Not sure this is 
directly related to the crash above, but it’s something that should 
be addressed regardless:

MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
		     infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014,
		     0, 1, -1, -1, -1),

I think __initconst should also be removed from clocks that are used at 
runtime. I’m not certain this is directly related to the issue, but I
wanted to mention it in case it’s helpful.

Best,

Laura

>
>> Gesendet: Sonntag, 21. September 2025 um 18:53
>> Von: "Stephen Boyd" <sboyd@...nel.org>
>> An: "Laura Nao" <laura.nao@...labora.com>, angelogioacchino.delregno@...labora.com, conor+dt@...nel.org, krzk+dt@...nel.org, matthias.bgg@...il.com, mturquette@...libre.com, p.zabel@...gutronix.de, richardcochran@...il.com, robh@...nel.org
>> CC: guangjie.song@...iatek.com, wenst@...omium.org, linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org, netdev@...r.kernel.org, kernel@...labora.com, "Laura Nao" <laura.nao@...labora.com>
>> Betreff: Re: [PATCH v6 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct
>>
>> Quoting Laura Nao (2025-09-15 08:19:26)
>>> MT8196 uses a HW voter for gate enable/disable control, with
>>> set/clr/sta registers located in a separate regmap. Refactor
>>> mtk_clk_register_gate() to take a struct mtk_gate, and add a pointer to
>>> it in struct mtk_clk_gate. This allows reuse of the static gate data
>>> (including HW voter register offsets) without adding extra function
>>> arguments, and removes redundant duplication in the runtime data struct.
>>>
>>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
>>> Reviewed-by: Chen-Yu Tsai <wenst@...omium.org>
>>> Signed-off-by: Laura Nao <laura.nao@...labora.com>
>>> ---
>>
>> Applied to clk-next
>