linux-kernel - Re: [PATCH] arm64: dts: freescale: imx93-phy{core, board}: Add i2c bus recovery

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Message-ID: <56075d3e-30ac-4501-bd77-2a84d0d124bd@pengutronix.de>
Date: Thu, 23 Oct 2025 14:00:46 +0200
From: Ahmad Fatoum <a.fatoum@...gutronix.de>
To: Primoz Fiser <primoz.fiser@...ik.com>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
 Sascha Hauer <s.hauer@...gutronix.de>,
 Pengutronix Kernel Team <kernel@...gutronix.de>,
 Fabio Estevam <festevam@...il.com>
Cc: devicetree@...r.kernel.org, upstream@...ts.phytec.de,
 linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 imx@...ts.linux.dev
Subject: Re: [PATCH] arm64: dts: freescale: imx93-phy{core, board}: Add i2c
 bus recovery

Hi,

On 10/23/25 12:34 PM, Primoz Fiser wrote:
> Add bus recovery feature for I2C buses on the PHYTEC phyCORE-i.MX93 SoM
> based boards (that is phyBOARD-Nash-i.MX93 and phyBOARD-Segin-i.MX93).
> This enables the i2c-imx-lpi2c driver to recover the stuck I2C bus by
> switching the SCL and SDA pinmuxing and do the I2C bus bit-banging.
> 
> Signed-off-by: Primoz Fiser <primoz.fiser@...ik.com>
> ---
>  .../arm64/boot/dts/freescale/imx93-phyboard-nash.dts | 12 +++++++++++-
>  .../boot/dts/freescale/imx93-phyboard-segin.dts      | 12 +++++++++++-
>  arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 12 +++++++++++-
>  3 files changed, 33 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts
> index 5599e296919f..96c58cf13754 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts
> @@ -128,8 +128,11 @@ &flexcan1 {
>  /* I2C2 */
>  &lpi2c2 {
>  	clock-frequency = <400000>;
> -	pinctrl-names = "default";
> +	pinctrl-names = "default", "gpio";
>  	pinctrl-0 = <&pinctrl_lpi2c2>;
> +	pinctrl-1 = <&pinctrl_lpi2c2_gpio>;
> +	scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
>  	status = "okay";
>  
>  	/* RTC */
> @@ -253,6 +256,13 @@ MX93_PAD_I2C2_SDA__LPI2C2_SDA		0x40000b9e
>  		>;
>  	};
>  
> +	pinctrl_lpi2c2_gpio: lpi2c2gpiogrp {
> +		fsl,pins = <
> +			MX93_PAD_I2C2_SCL__GPIO1_IO02		0x31e

I haven't worked with imx93 myself yet, but does this not need the SION
bit set?

Cheers,
Ahmad

> +			MX93_PAD_I2C2_SDA__GPIO1_IO03		0x31e
> +		>;
> +	};
> +
>  	pinctrl_lpspi6: lpspi6grp {
>  		fsl,pins = <
>  			MX93_PAD_GPIO_IO00__GPIO2_IO00		0x386
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> index 802d96b19e4c..1850a93dbaa4 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> @@ -132,8 +132,11 @@ &flexcan1 {
>  /* I2C2 */
>  &lpi2c2 {
>  	clock-frequency = <400000>;
> -	pinctrl-names = "default";
> +	pinctrl-names = "default", "gpio";
>  	pinctrl-0 = <&pinctrl_lpi2c2>;
> +	pinctrl-1 = <&pinctrl_lpi2c2_gpio>;
> +	scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
>  	status = "okay";
>  
>  	/* Codec */
> @@ -238,6 +241,13 @@ MX93_PAD_I2C2_SDA__LPI2C2_SDA		0x40000b9e
>  		>;
>  	};
>  
> +	pinctrl_lpi2c2_gpio: lpi2c2gpiogrp {
> +		fsl,pins = <
> +			MX93_PAD_I2C2_SCL__GPIO1_IO02		0x31e
> +			MX93_PAD_I2C2_SDA__GPIO1_IO03		0x31e
> +		>;
> +	};
> +
>  	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
>  		fsl,pins = <
>  			MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x31e
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> index 3f069905cf0b..ebc57841f27f 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> @@ -93,8 +93,11 @@ ethphy1: ethernet-phy@1 {
>  /* I2C3 */
>  &lpi2c3 {
>  	clock-frequency = <400000>;
> -	pinctrl-names = "default";
> +	pinctrl-names = "default", "gpio";
>  	pinctrl-0 = <&pinctrl_lpi2c3>;
> +	pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
> +	scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
>  	status = "okay";
>  
>  	pmic@25 {
> @@ -234,6 +237,13 @@ MX93_PAD_GPIO_IO29__LPI2C3_SCL		0x40000b9e
>  		>;
>  	};
>  
> +	pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {
> +		fsl,pins = <
> +			MX93_PAD_GPIO_IO28__GPIO2_IO28		0x31e
> +			MX93_PAD_GPIO_IO29__GPIO2_IO29		0x31e
> +		>;
> +	};
> +
>  	pinctrl_pmic: pmicgrp {
>  		fsl,pins = <
>  			MX93_PAD_ENET2_RD3__GPIO4_IO27		0x31e

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