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Message-ID: <kbbebw2kr3hu6q3sb4z3i7yy7vv432rjx2ylp254cbifpcxe33@bhyldim36fff>
Date: Thu, 23 Oct 2025 15:14:37 +0300
From: Abel Vesa <abel.vesa@...aro.org>
To: Sarthak Garg <sarthak.garg@....qualcomm.com>
Cc: Ulf Hansson <ulf.hansson@...aro.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>,
linux-mmc@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-msm@...r.kernel.org, quic_nguyenb@...cinc.com, quic_rampraka@...cinc.com,
quic_pragalla@...cinc.com, quic_sayalil@...cinc.com, quic_nitirawa@...cinc.com,
quic_bhaskarv@...cinc.com, kernel@....qualcomm.com
Subject: Re: [PATCH V2 2/4] arm64: dts: qcom: sm8750: Add SDC2 nodes for
sm8750 soc
On 25-10-23 16:59:22, Sarthak Garg wrote:
> Add SD Card host controller for sm8750 soc.
>
> Signed-off-by: Sarthak Garg <sarthak.garg@....qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/sm8750.dtsi | 68 ++++++++++++++++++++++++++++
> 1 file changed, 68 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index a82d9867c7cb..1070dc5ea196 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -2060,6 +2060,60 @@ ice: crypto@...8000 {
> clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
> };
>
> + sdhc_2: mmc@...4000 {
> + compatible = "qcom,sm8750-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0 0x08804000 0 0x1000>;
> +
> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq",
> + "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC2_AHB_CLK>,
> + <&gcc GCC_SDCC2_APPS_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface",
> + "core",
> + "xo";
> +
> + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
> + interconnect-names = "sdhc-ddr",
> + "cpu-sdhc";
> +
> + power-domains = <&rpmhpd RPMHPD_CX>;
> + operating-points-v2 = <&sdhc2_opp_table>;
> +
> + qcom,dll-config = <0x0007442c>;
> + qcom,ddr-config = <0x80040868>;
> +
> + iommus = <&apps_smmu 0x540 0x0>;
> + dma-coherent;
> +
> + bus-width = <4>;
> + max-sd-hs-hz = <37500000>;
> +
> + resets = <&gcc GCC_SDCC2_BCR>;
> +
> + status = "disabled";
> +
> + sdhc2_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-202000000 {
> + opp-hz = /bits/ 64 <202000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> + };
> + };
> +
> cryptobam: dma-controller@...4000 {
> compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
> reg = <0x0 0x01dc4000 0x0 0x28000>;
> @@ -3121,6 +3175,13 @@ data-pins {
> drive-strength = <2>;
> bias-pull-up;
> };
> +
> + card-detect-pins {
> + pins = "gpio55";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
These are board specific, so move them to the board dts.
> };
>
> sdc2_default: sdc2-default-state {
> @@ -3141,6 +3202,13 @@ data-pins {
> drive-strength = <10>;
> bias-pull-up;
> };
> +
> + card-detect-pins {
> + pins = "gpio55";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
Ditto.
> };
> };
>
> --
> 2.34.1
>
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