linux-kernel - Re: [PATCH v2 5/5] clk: samsung: introduce exynos8890 clock driver

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Message-ID: <CADrjBPpmUzu=g7RfJShC_2VNnvAt9Ur5NrGbyctssyMQ0nPkmg@mail.gmail.com>
Date: Fri, 24 Oct 2025 14:51:06 +0100
From: Peter Griffin <peter.griffin@...aro.org>
To: Ivaylo Ivanov <ivo.ivanov.ivanov1@...il.com>
Cc: Krzysztof Kozlowski <krzk@...nel.org>, Sylwester Nawrocki <s.nawrocki@...sung.com>, 
	Chanwoo Choi <cw00.choi@...sung.com>, Alim Akhtar <alim.akhtar@...sung.com>, 
	Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Rob Herring <robh@...nel.org>, Conor Dooley <conor+dt@...nel.org>, linux-samsung-soc@...r.kernel.org, 
	linux-clk@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 5/5] clk: samsung: introduce exynos8890 clock driver

Hi Ivaylo,

On Fri, 24 Oct 2025 at 13:34, Ivaylo Ivanov
<ivo.ivanov.ivanov1@...il.com> wrote:
>
> On 10/24/25 15:07, Peter Griffin wrote:
> > Hi Ivaylo & Krzysztof,
> >
> > On Wed, 22 Oct 2025 at 08:56, Krzysztof Kozlowski <krzk@...nel.org> wrote:
> >> On Fri, Oct 17, 2025 at 07:13:33PM +0300, Ivaylo Ivanov wrote:
> >>> Introduce a clocks management driver for exynos8890, providing clocks
> >>> for the peripherals of that SoC.
> >>>
> >>> As exynos8890 is the first exynos SoC to feature Hardware Auto Clock
> >>> Gating (HWACG), it differs from newer SoCs. Q-channel and Q-state bits
> >>> are separate registers, unlike the CLK_CON_GAT_* ones that feature HWACG
> >>> bits in the same register that controls manual gating. Hence, don't use
> >>> the clk-exynos-arm64 helper, but implement logic that enforces manual
> >>> gating.
> > For sure it isn't the only upstream SoC with HWACG, gs101 and e850 and
> > probably lots of Exynos SoCs have it. Whether it is the "first" in
> > terms of release date of the SoC I don't know
>
> Huh? Samsung hasn't released a lot of exynos chips and you're free to check
> kernel sources if curious. Exynos 7420 didn't have HWACG, 8890 and 8895
> have it. Exynos 7870 (roughly same gen as 8890, but budget lineup) doesn't
> have it.

I'll take your word for it!
>
> > , unless there is some comment in
> > downstream code to that effect). Your CMU registers do look like a
> > different layout though.
>
> Exactly. First implementation/gen of HWACG == lots of room to improve.
> Which they did, and this is what I implied here. I can word it differently
> though, to be more clear.

Ok, that makes sense. If it can be slightly reworded to make that
clearer, as I found it slightly ambiguous on "first read".

>
> > Just fyi gs101 also has Q-Channel registers that contain HWACG Enable
> > bits. The reset state of all these bits on gs101 (both for QCH_CON_XXX
> > registers, QCH_EN bit and HWACG bit in CLK_CON_GAT_* regs is off). In
> > my case I suspect the bootloader doesn't initialize any of them
> > because of the CMUs "global enable override" bits in the CMU_OPTION
> > register (which is initialized by the bootloader).
>
> Well, to be fair, without any documentations or bootloader sources there's
> so much so I can do. The vendor kernel also force disables the qchannel
> registers, hence the assumption.

Sure, I appreciate having no specs and only downstream kernel sources
is tough going. I think it's great what you folks are doing under the
circumstances! I just wanted to point out that having some HWACG bits
in the QCH regs isn't unique to this SoC (although it would seem that
having to initialize all of the registers possibly is). Maybe the
HWACG "global override" bits is one of the things they added in future
revisions of HWACG.

regards,

Peter