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Message-ID: <CAPDyKFqGwTF2w2JfqOuxMt6m_YJOYhqoUaQXyZALRu94W3fGkQ@mail.gmail.com>
Date: Fri, 24 Oct 2025 15:57:33 +0200
From: Ulf Hansson <ulf.hansson@...aro.org>
To: hehuan1@...incomputing.com, robh@...nel.org, krzk+dt@...nel.org
Cc: conor+dt@...nel.org, jszhang@...nel.org, adrian.hunter@...el.com,
p.zabel@...gutronix.de, linux-mmc@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, ningyu@...incomputing.com,
linmin@...incomputing.com, pinkesh.vaghela@...fochips.com,
xuxiang@...incomputing.com, luyulin@...incomputing.com,
dongxuyang@...incomputing.com, zhangsenchuan@...incomputing.com,
weishangjuan@...incomputing.com, lizhi2@...incomputing.com,
caohang@...incomputing.com, Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [PATCH v5 1/2] dt-bindings: mmc: sdhci-of-dwcmshc: Add Eswin EIC7700
On Sun, 19 Oct 2025 at 13:52, <hehuan1@...incomputing.com> wrote:
>
> From: Huan He <hehuan1@...incomputing.com>
>
> EIC7700 use Synopsys dwcmshc IP for SD/eMMC controllers.
> Add Eswin EIC7700 support in sdhci-of-dwcmshc.yaml.
>
> Signed-off-by: Huan He <hehuan1@...incomputing.com>
> Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
> ---
> .../bindings/mmc/snps,dwcmshc-sdhci.yaml | 57 +++++++++++++++++--
> 1 file changed, 51 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
> index f882219a0a26..7e7c55dc2440 100644
> --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
> +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
> @@ -30,6 +30,7 @@ properties:
> - sophgo,sg2002-dwcmshc
> - sophgo,sg2042-dwcmshc
> - thead,th1520-dwcmshc
> + - eswin,eic7700-dwcmshc
>
> reg:
> maxItems: 1
> @@ -52,17 +53,30 @@ properties:
> maxItems: 5
>
> reset-names:
> - items:
> - - const: core
> - - const: bus
> - - const: axi
> - - const: block
> - - const: timer
> + maxItems: 5
>
> rockchip,txclk-tapnum:
> description: Specify the number of delay for tx sampling.
> $ref: /schemas/types.yaml#/definitions/uint8
>
> + eswin,hsp-sp-csr:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: Phandle to HSP(High-Speed Peripheral) device
> + - description: Offset of the stability status register for internal
> + clock.
> + - description: Offset of the stability register for host regulator
> + voltage.
> + description:
> + HSP CSR is to control and get status of different high-speed peripherals
> + (such as Ethernet, USB, SATA, etc.) via register, which can tune
> + board-level's parameters of PHY, etc.
I would like second confirmation from DT maintainers, to make sure
it's reasonable to model the HW like this.
In principle the phandle above gets translated into a regmap via a
call to syscon_node_to_regmap() in the driver, to allow some registers
to be written that are outside the controllers address space.
> +
> + eswin,drive-impedance-ohms:
> + description: Specifies the drive impedance in Ohm.
> + enum: [33, 40, 50, 66, 100]
> +
> required:
> - compatible
> - reg
> @@ -110,6 +124,37 @@ allOf:
> - const: block
> - const: timer
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: eswin,eic7700-dwcmshc
> + then:
> + properties:
> + resets:
> + minItems: 4
> + maxItems: 4
> + reset-names:
> + items:
> + - const: axi
> + - const: phy
> + - const: prstn
> + - const: txrx
> + required:
> + - eswin,hsp-sp-csr
> + - eswin,drive-impedance-ohms
> + else:
> + properties:
> + resets:
> + maxItems: 5
> + reset-names:
> + items:
> + - const: core
> + - const: bus
> + - const: axi
> + - const: block
> + - const: timer
> +
> - if:
> properties:
> compatible:
> --
> 2.25.1
>
Kind regards
Uffe
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