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Message-ID: <20251024143423.GF847003@nvidia.com>
Date: Fri, 24 Oct 2025 11:34:23 -0300
From: Jason Gunthorpe <jgg@...dia.com>
To: Wei Wang <wei.w.wang@...mail.com>
Cc: "suravee.suthikulpanit@....com" <suravee.suthikulpanit@....com>,
"thomas.lendacky@....com" <thomas.lendacky@....com>,
"joro@...tes.org" <joro@...tes.org>,
"kevin.tian@...el.com" <kevin.tian@...el.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"iommu@...ts.linux.dev" <iommu@...ts.linux.dev>
Subject: Re: [PATCH v1] iommu/amd: Set C-bit only for RAM-backed PTEs in
IOMMU page tables
On Fri, Oct 24, 2025 at 02:23:54PM +0000, Wei Wang wrote:
> > Again we should not be trying to guess if something is "ram" or not
> > deep inside the iommu code. We have IOMMU_MMIO specifically to tell
> > the iommu if it is ram or not.
>
> Sorry I think my main confusion here is why this is considered a ‘guess’ of RAM.
> The function page_is_ram() clearly returns whether it is RAM, right?
IIRC it is not reliable. We have a lot of things in modern systems
that are cachable ram-like objects that page_is_ram() may or may not
return true on.
Further, page_is_ram is very expensive:
int __weak page_is_ram(unsigned long pfn)
{
return walk_system_ram_range(pfn, 1, NULL, __is_ram) == 1;
We really don't want to be doing something like that for every IOMMU
PTE.
For your immediate problem IOMMU_MMIO is better, but broadly I think
this will need some attention later. I'm not sure how something like
CXL cachable ram is supposed to work through these APIs, or if it
should have the C bit set.
Jason
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