linux-kernel - Re: [PATCH] PCI/ASPM: Enable only L0s and L1 for devicetree platforms

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Message-ID: <20251024203924.GA1361677@bhelgaas>
Date: Fri, 24 Oct 2025 15:39:24 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: Johan Hovold <johan@...nel.org>
Cc: linux-pci@...r.kernel.org,
	Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>,
	Christian Zigotzky <chzigotzky@...osoft.de>,
	FUKAUMI Naoki <naoki@...xa.com>,
	Herve Codina <herve.codina@...tlin.com>,
	Diederik de Haas <diederik@...ow-tech.com>,
	Dragan Simic <dsimic@...jaro.org>, linuxppc-dev@...ts.ozlabs.org,
	linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Shawn Lin <shawn.lin@...k-chips.com>, Frank Li <Frank.li@....com>
Subject: Re: [PATCH] PCI/ASPM: Enable only L0s and L1 for devicetree platforms

[+cc Shawn, Frank]

On Fri, Oct 24, 2025 at 05:20:33PM +0200, Johan Hovold wrote:
> On Fri, Oct 24, 2025 at 05:12:38PM +0200, Johan Hovold wrote:
> > On Thu, Oct 23, 2025 at 01:06:26PM -0500, Bjorn Helgaas wrote:
> > > From: Bjorn Helgaas <bhelgaas@...gle.com>
> > > 
> > > f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for
> > > devicetree platforms") enabled Clock Power Management and L1 PM
> > > Substates, but those features depend on CLKREQ# and possibly
> > > other device-specific configuration.  We don't know whether
> > > CLKREQ# is supported, so we shouldn't blindly enable Clock PM
> > > and L1 PM Substates.
> > > 
> > > Enable only ASPM L0s and L1, and only when both ends of the link
> > > advertise support for them.
> > > 
> > > Fixes: f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms")
> ...

> > > ---
> > > I intend this for v6.18-rc3.
> > 
> > Note that this will regress ASPM on Qualcomm platforms further by
> > disabling L1SS for devices that do not use pwrctrl (e.g. NVMe). ASPM
> > with pwrctrl is already broken since 6.15. [1]
> 
> Actually, the 6.15 regression was fixed in 6.18-rc1 by the offending
> commit, but pwrctrl devices will now also regress again.
> 
> > Reverting also a729c1664619 ("PCI: qcom: Remove custom ASPM enablement
> > code") should avoid the new regression until a proper fix for the 6.15
> > regression is in place.

Help me think through this.  I just sent a pull request [2] that
includes df5192d9bb0e ("PCI/ASPM: Enable only L0s and L1 for
devicetree platforms").  If all goes well, v6.18-rc3 will enable L0s
and L1 (but not L1SS) on Qualcomm platforms.

IIUC, if we then revert a729c1664619 ("PCI: qcom: Remove custom ASPM
enablement code"), it will enable L1SS again, but since this is done
in a dw_pcie_host_ops .post_init() hook, L1SS will only be enabled for
devices powered on at qcom-pcie probe time.  It will *not* be enabled
for pwrctrl devices because .post_init() was run when those devices
were powered off.

I think this is the same as in v6.17.  v6.18-rc1 enabled L1SS for
everything, including pwrctrl devices, because it was done in the PCI
enumeration path, not the host controller probe path.  I think that
enumeration is the right place to do this, but we need to figure out
how to do it in a generic way.  At a minimum, we need to know that
CLKREQ# is supported, and some platforms like dw-rockchip also need
device-specific configuration [3].

Bottom line, I think we need to revert a729c1664619 for v6.18 to get
all ASPM states including L1SS enabled on Qualcomm platforms for
non-pwrctrl devices.  I'll post a patch for this.

Then try to figure out how to make this work for pwrctrl devices for
v6.19.  Does this sound right?

Bjorn

> > [1] https://lore.kernel.org/lkml/aH4JPBIk_GEoAezy@hovoldconsulting.com/

[2] https://lore.kernel.org/r/20251024192903.GA1360890@bhelgaas
[3] https://lore.kernel.org/r/1761187883-150120-1-git-send-email-shawn.lin@rock-chips.com