linux-kernel - Re: [PATCH v6 4/5] PCI/ERR: Use pcie_aer_is_native() to check for native AER control

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Message-ID: <2cc91a94-a444-4d15-b714-fe8502da1586@linux.alibaba.com>
Date: Fri, 24 Oct 2025 13:37:37 +0800
From: Shuai Xue <xueshuai@...ux.alibaba.com>
To: Lukas Wunner <lukas@...ner.de>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>, linux-pci@...r.kernel.org,
 linux-kernel@...r.kernel.org, linuxppc-dev@...ts.ozlabs.org,
 kbusch@...nel.org, sathyanarayanan.kuppuswamy@...ux.intel.com,
 mahesh@...ux.ibm.com, oohall@...il.com, Jonathan.Cameron@...wei.com,
 terry.bowman@....com, tianruidong@...ux.alibaba.com
Subject: Re: [PATCH v6 4/5] PCI/ERR: Use pcie_aer_is_native() to check for
 native AER control



在 2025/10/24 12:03, Lukas Wunner 写道:
> On Fri, Oct 24, 2025 at 11:38:10AM +0800, Shuai Xue wrote:
>> The remaining question is whether it would make more sense to rename
>> pcie_clear_device_status() to pci_clear_device_error_status() and refine
>> its behavior by adding a mask specifically for bits 0 to 3. Here's an
>> example of the proposed change:
> 
> I don't see much value in renaming the function.
> 
> However clearing only bits 0-3 makes sense.  PCIe r5.0 defined bit 6
> as Emergency Power Reduction Detected with type RW1C in 2019.  The
> last time we touched pcie_clear_device_status() was in 2018 with
> ec752f5d54d7 and we've been clearing all bits since forever,
> not foreseeing that new ones with type RW1C might be added later.

Thank you for the detailed explanation and pointing out the history
behind bit 6 and the evolution since PCIe r5.0.

> 
> I suggest defining a new macro in include/uapi/linux/pci_regs.h
> instead of using 0xf, say PCI_EXP_DEVSTA_ERR.  Then you don't
> need the code comment because the code is self-explanatory.
> 

I’ll prepare a patch to implement this fix and submit it shortly.
Thanks again for the guidance!

Thanks.
Shuai