linux-kernel - Re: [PATCH 1/6] drm/msm/a6xx: Add support for Adreno 612

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Message-ID: <5e64c246-a424-42c9-b102-e1a2af579936@oss.qualcomm.com>
Date: Fri, 24 Oct 2025 09:55:29 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Akhil P Oommen <akhilpo@....qualcomm.com>,
        Rob Clark <robin.clark@....qualcomm.com>, Sean Paul <sean@...rly.run>,
        Konrad Dybcio <konradybcio@...nel.org>,
        Dmitry Baryshkov <lumag@...nel.org>,
        Abhinav Kumar <abhinav.kumar@...ux.dev>,
        Jessica Zhang <jessica.zhang@....qualcomm.com>,
        Marijn Suijten <marijn.suijten@...ainline.org>,
        David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
        Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
        Maxime Ripard <mripard@...nel.org>,
        Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
        freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, Jie Zhang <quic_jiezh@...cinc.com>
Subject: Re: [PATCH 1/6] drm/msm/a6xx: Add support for Adreno 612

On 10/24/25 12:57 AM, Akhil P Oommen wrote:
> On 10/22/2025 8:43 PM, Konrad Dybcio wrote:
>> On 10/17/25 7:08 PM, Akhil P Oommen wrote:
>>> From: Jie Zhang <quic_jiezh@...cinc.com>
>>>
>>> Add support for Adreno 612 GPU found in SM6150/QCS615 chipsets.
>>> A612 falls under ADRENO_6XX_GEN1 family and is a cut down version
>>> of A615 GPU.
>>>
>>> A612 has a new IP called Reduced Graphics Management Unit or RGMU
>>> which is a small state machine which helps to toggle GX GDSC
>>> (connected to CX rail) to implement IFPC feature. It doesn't support
>>> any other features of a full fledged GMU like clock control, resource
>>> voting to rpmh etc. So we need linux clock driver support like other
>>> gmu-wrapper implementations to control gpu core clock and gpu GX gdsc.
>>> This patch skips RGMU core initialization and act more like a
>>> gmu-wrapper case.
>>>
>>> Co-developed-by: Akhil P Oommen <akhilpo@....qualcomm.com>
>>> Signed-off-by: Jie Zhang <quic_jiezh@...cinc.com>
>>> Signed-off-by: Akhil P Oommen <akhilpo@....qualcomm.com>
>>> ---
>>
>> [...]
>>
>>> @@ -350,12 +350,18 @@ static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = {
>>>  /* Trigger a OOB (out of band) request to the GMU */
>>>  int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
>>>  {
>>> +	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
>>> +	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
>>>  	int ret;
>>>  	u32 val;
>>>  	int request, ack;
>>>  
>>>  	WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
>>>  
>>> +	/* Skip OOB calls since RGMU is not enabled */
>>
>> "RGMU doesn't handle OOB calls"
> 
> Technically RGMU can handle OOB calls. But we are not initializing rgmu.

Oh, I glossed over that..

IIRC the reason we delayed 612 support in the past was to make sure
that the RGMU FW is consumed, so that runtime requirements don't
suddenly change one day.

If you have no interest/way in getting it wholly supported right now,
can you at least make sure that the driver requests the firmware and
exits if it's absent?

Konrad