linux-kernel - [PATCH v1 7/7] clk: mediatek: Add support for MT6685 PM/Clock IC Clock Controller

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Message-ID: <20251024083301.25845-8-angelogioacchino.delregno@collabora.com>
Date: Fri, 24 Oct 2025 10:33:01 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: sboyd@...nel.org
Cc: mturquette@...libre.com,
	robh@...nel.org,
	krzk+dt@...nel.org,
	conor+dt@...nel.org,
	matthias.bgg@...il.com,
	angelogioacchino.delregno@...labora.com,
	laura.nao@...labora.com,
	nfraprado@...labora.com,
	wenst@...omium.org,
	y.oudjana@...tonmail.com,
	linux-clk@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-mediatek@...ts.infradead.org,
	kernel@...labora.com
Subject: [PATCH v1 7/7] clk: mediatek: Add support for MT6685 PM/Clock IC Clock Controller

Add support for the SCK_TOP Clock Controller IP found in the
MediaTek MT6685 PM/Clock IC as a SPMI Sub-Device.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
---
 drivers/clk/mediatek/Kconfig      |  7 ++++
 drivers/clk/mediatek/Makefile     |  2 +
 drivers/clk/mediatek/clk-mt6685.c | 70 +++++++++++++++++++++++++++++++
 3 files changed, 79 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt6685.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 3452dcbc9e45..eb1764418b1e 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -132,6 +132,13 @@ config COMMON_CLK_MT2712_VENCSYS
 	help
 	  This driver supports MediaTek MT2712 vencsys clocks.
 
+config COMMON_CLK_MT6685
+	tristate "Clock driver for MediaTek MT6685 Clock IC"
+	depends on ARCH_MEDIATEK
+	select COMMON_CLK_MEDIATEK_SPMI
+	help
+	  This driver supports clocks provided by the MT6685 Clock IC.
+
 config COMMON_CLK_MT6735
 	tristate "Main clock drivers for MediaTek MT6735"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 1471d8affa44..d68837f1aa06 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -5,6 +5,8 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mediatek.o
 
 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
 
+obj-$(CONFIG_COMMON_CLK_MT6685) += clk-mt6685.o
+
 obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o
 obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) += clk-mt6735-imgsys.o
 obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) += clk-mt6735-mfgcfg.o
diff --git a/drivers/clk/mediatek/clk-mt6685.c b/drivers/clk/mediatek/clk-mt6685.c
new file mode 100644
index 000000000000..1d524aef61a5
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6685.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 Collabora Ltd.
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
+ */
+#include <dt-bindings/clock/mediatek,mt6685-clock.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+#include "clk-mtk-spmi.h"
+#include "reset.h"
+
+static const struct mtk_gate_regs spmi_mt6685_sck_top_cg_regs = {
+	.set_ofs = 0x1,
+	.clr_ofs = 0x2,
+	.sta_ofs = 0x0
+};
+
+#define GATE_SCKTOP(_id, _name, _parent, _shift)	\
+{							\
+	.id = _id,					\
+	.name = _name,					\
+	.parent_name = _parent,				\
+	.regs = &spmi_mt6685_sck_top_cg_regs,		\
+	.shift = _shift,				\
+	.flags = CLK_IGNORE_UNUSED,			\
+	.ops = &mtk_clk_gate_ops_setclr,		\
+}
+
+static const struct mtk_gate sck_top_clks[] = {
+	GATE_SCKTOP(CLK_RTC_SEC_MCLK, "rtc_sec_mclk", "rtc_sec_32k", 0),
+	GATE_SCKTOP(CLK_RTC_EOSC32, "rtc_eosc32", "clk26m", 2),
+	GATE_SCKTOP(CLK_RTC_SEC_32K, "rtc_sec_32k", "clk26m", 3),
+	GATE_SCKTOP(CLK_RTC_MCLK, "rtc_mclk", "rtc_32k", 4),
+	GATE_SCKTOP(CLK_RTC_32K, "rtc_32k", "clk26m", 5),
+};
+
+static const struct mtk_clk_desc mt6685_sck_top_mcd = {
+	.clks = sck_top_clks,
+	.num_clks = ARRAY_SIZE(sck_top_clks),
+};
+
+static const struct mtk_spmi_clk_desc mt6685_sck_top_mscd = {
+	.desc = &mt6685_sck_top_mcd,
+	.max_register = 0x10,
+};
+
+static const struct of_device_id of_match_clk_mt6685[] = {
+	{ .compatible = "mediatek,mt6685-sck-top", .data = &mt6685_sck_top_mscd },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt6685);
+
+static struct platform_driver clk_mt6685_spmi_drv = {
+	.probe = mtk_spmi_clk_simple_probe,
+	.remove = mtk_clk_simple_remove,
+	.driver = {
+		.name = "clk-spmi-mt6685",
+		.of_match_table = of_match_clk_mt6685,
+	},
+};
+module_platform_driver(clk_mt6685_spmi_drv);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>");
+MODULE_DESCRIPTION("MediaTek MT6685 SPMI Clock IC clocks driver");
+MODULE_LICENSE("GPL");
-- 
2.51.1