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Message-Id: <20251024114845.2395166-2-pritam.sutar@samsung.com>
Date: Fri, 24 Oct 2025 17:18:43 +0530
From: Pritam Manohar Sutar <pritam.sutar@...sung.com>
To: robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
alim.akhtar@...sung.com
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org,
rosa.pila@...sung.com, dev.tailor@...sung.com, faraz.ata@...sung.com,
muhammed.ali@...sung.com, selvarasu.g@...sung.com, pritam.sutar@...sung.com
Subject: [PATCH 1/3] arm64: dts: exynos: ExynosAutov920: Add USB and USB-phy
nodes
Add USB and USB PHY controller nodes.
Signed-off-by: Pritam Manohar Sutar <pritam.sutar@...sung.com>
---
.../arm64/boot/dts/exynos/exynosautov920.dtsi | 162 ++++++++++++++++++
1 file changed, 162 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index 6ee74d260776..6ff0e00fd901 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -1409,6 +1409,168 @@ pinctrl_hsi1: pinctrl@...50000 {
interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
};
+ usbdrd31_ssphy: phy@...80000 {
+ compatible = "samsung,exynosautov920-usb31drd-combo-ssphy";
+ reg = <0x16480000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ usbdrd31_hsphy: phy@...90000 {
+ compatible = "samsung,exynosautov920-usbdrd-combo-hsphy";
+ reg = <0x16490000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ usbdrd20_phy0: phy@...00000 {
+ compatible = "samsung,exynosautov920-usbdrd-phy";
+ reg = <0x16500000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ usbdrd20_phy1: phy@...10000 {
+ compatible = "samsung,exynosautov920-usbdrd-phy";
+ reg = <0x16510000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ usbdrd20_phy2: phy@...20000 {
+ compatible = "samsung,exynosautov920-usbdrd-phy";
+ reg = <0x16520000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ /* This usb port supports usb31 and usb20 speeds */
+ usbdrd31: usb@...00000 {
+ compatible = "samsung,exynosautov920-dwusb3";
+ ranges = <0x0 0x16600000 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usbdrd31_dwc3: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ interrupts = <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd31_hsphy 0>, <&usbdrd31_ssphy 0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ snps,has-lpm-erratum;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
+ /* This usb port supports only usb20 speeds */
+ usbdrd20_0: usb@...00000 {
+ compatible = "samsung,exynosautov920-dwusb3";
+ ranges = <0x0 0x16700000 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usbdrd20_dwc3_0: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd20_phy0 0>;
+ phy-names = "usb2-phy";
+ snps,has-lpm-erratum;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ };
+ };
+
+ /* This usb port supports only usb20 speeds */
+ usbdrd20_1: usb@...00000 {
+ compatible = "samsung,exynosautov920-dwusb3";
+ ranges = <0x0 0x16800000 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usbdrd20_dwc3_1: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd20_phy1 0>;
+ phy-names = "usb2-phy";
+ snps,has-lpm-erratum;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ };
+ };
+
+ /* This usb port supports only usb20 speeds */
+ usbdrd20_2: usb@...00000 {
+ compatible = "samsung,exynosautov920-dwusb3";
+ ranges = <0x0 0x16900000 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usbdrd20_dwc3_2: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ interrupts = <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd20_phy2 0>;
+ phy-names = "usb2-phy";
+ snps,has-lpm-erratum;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ };
+ };
+
cmu_hsi2: clock-controller@...00000 {
compatible = "samsung,exynosautov920-cmu-hsi2";
reg = <0x16b00000 0x8000>;
--
2.34.1
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