linux-kernel - [PATCH v2 0/6] clk/reset: anlogic: add support for DR1V90 SoC

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Message-Id: <20251026-dr1v90-cru-v2-0-43b67acd6ddd@pigmoral.tech>
Date: Sun, 26 Oct 2025 22:00:40 +0800
From: Junhui Liu <junhui.liu@...moral.tech>
To: Michael Turquette <mturquette@...libre.com>, 
 Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de>, 
 Junhui Liu <junhui.liu@...moral.tech>, Paul Walmsley <pjw@...nel.org>, 
 Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
 Alexandre Ghiti <alex@...ti.fr>
Cc: linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, 
 linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org, 
 Troy Mitchell <troy.mitchell@...ux.spacemit.com>, 
 Conor Dooley <conor.dooley@...rochip.com>
Subject: [PATCH v2 0/6] clk/reset: anlogic: add support for DR1V90 SoC

This adds Clock and Reset Unit (CRU) support for the Anlogic DR1V90 SoC,
as well as corresponding dts bindings and dts integration.

The CRU driver framework is built around the clock controller as the
primary device, with the reset controller implemented as an auxiliary
device. The clock part refers to the vendor's code [1] to determine the
structure of the clock tree.

The Anlogic DR1 series includes not only the DR1V90 (based on the Nuclei
UX900 RISC-V core), but also the DR1M90 (based on the Cortex-A35 ARM64
core). Most of the clock tree and CRU design can be shared between them.
This series only adds CRU support for DR1V90. Nevertheless, the driver
is structured to make future extension to other DR1 variants like
DR1M90.

This depends on the basic dt series for DR1V90 SoC [2].

Link: https://gitee.com/anlogic/linux/blob/anlogic-6.1.54/drivers/clk/anlogic/anl_dr1x90_crp.c [1]
Link: https://lore.kernel.org/all/20251021-dr1v90-basic-dt-v3-0-5478db4f664a@pigmoral.tech/ [2]
---
Changes in v2:
- Update copyright infomation
- Add the original vendor author's infomation to the clock driver
- Rebase on the v3 basic DT patch, which is based on v6.18-rc1
- Link to v1: https://lore.kernel.org/r/20250922-dr1v90-cru-v1-0-e393d758de4e@pigmoral.tech

---
Junhui Liu (6):
      clk: correct clk_div_mask() return value for width == 32
      dt-bindings: clock: add Anlogic DR1V90 CRU
      clk: anlogic: add cru support for Anlogic DR1V90 SoC
      reset: anlogic: add support for Anlogic DR1V90 resets
      riscv: dts: anlogic: add clocks and CRU for DR1V90
      MAINTAINERS: Add entry for Anlogic DR1V90 SoC drivers

 .../bindings/clock/anlogic,dr1v90-cru.yaml         |  60 +++++
 MAINTAINERS                                        |   7 +
 arch/riscv/boot/dts/anlogic/dr1v90.dtsi            |  41 +++-
 drivers/clk/Kconfig                                |   1 +
 drivers/clk/Makefile                               |   1 +
 drivers/clk/anlogic/Kconfig                        |   9 +
 drivers/clk/anlogic/Makefile                       |   5 +
 drivers/clk/anlogic/cru-dr1v90.c                   | 191 +++++++++++++++
 drivers/clk/anlogic/cru_dr1.c                      | 258 +++++++++++++++++++++
 drivers/clk/anlogic/cru_dr1.h                      | 117 ++++++++++
 drivers/reset/Kconfig                              |   9 +
 drivers/reset/Makefile                             |   1 +
 drivers/reset/reset-dr1v90.c                       | 135 +++++++++++
 include/dt-bindings/clock/anlogic,dr1v90-cru.h     |  46 ++++
 include/dt-bindings/reset/anlogic,dr1v90-cru.h     |  41 ++++
 include/linux/clk-provider.h                       |   2 +-
 16 files changed, 921 insertions(+), 3 deletions(-)
---
base-commit: cb6649f6217c0331b885cf787f1d175963e2a1d2
change-id: 20250922-dr1v90-cru-74ab40c7f273
prerequisite-message-id: <20251021-dr1v90-basic-dt-v3-0-5478db4f664a@...moral.tech>
prerequisite-patch-id: dc2c18c600b0efd0e3237c11b580cb011b3f5070
prerequisite-patch-id: d67ae8ee7c8f7dcb35dc7417d002b1d9cb4d928d
prerequisite-patch-id: ab3aa9ae32dee038edbee3fd0c809fe4bb724d1c
prerequisite-patch-id: 8449f95ede2e21e6e545fcf8cbe24d6cfe204bfc
prerequisite-patch-id: 3aea99ba3c003e8604b20524b785eebb62f837b5
prerequisite-patch-id: bcda9d5f27158bf498cbf63fb9a5cc748d84b02a
prerequisite-patch-id: 21df177b6e5bfe62e9bb698a4fcfe1edc5484ab4
prerequisite-patch-id: 2c6db06e8d61a46fbd68f6ecc49e111ad0e5f145
prerequisite-patch-id: 3dfbda7104f6b4eb1fe681819209d0731f00edf3
prerequisite-patch-id: d2e029f574d4c2e328b8f6f7cdbb415b1bdb8f80
prerequisite-patch-id: 069c680b37c2906bf32f8aec1f7b2256889744e4
prerequisite-patch-id: e5df216772233d916cf88a55de52b06ef0d66222
prerequisite-patch-id: 72df5f2d85ee2234887ad66d38be3dff51439346

Best regards,
-- 
Junhui Liu <junhui.liu@...moral.tech>