[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <176151483790.2985487.5387793525895332800.robh@kernel.org>
Date: Sun, 26 Oct 2025 16:40:41 -0500
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Junhui Liu <junhui.liu@...moral.tech>
Cc: Daniel Lezcano <daniel.lezcano@...aro.org>,
Paul Walmsley <pjw@...nel.org>, linux-serial@...r.kernel.org,
Thomas Gleixner <tglx@...utronix.de>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-riscv@...ts.infradead.org, Albert Ou <aou@...s.berkeley.edu>,
Jiri Slaby <jirislaby@...nel.org>,
Chen Wang <unicorn_wang@...look.com>, devicetree@...r.kernel.org,
Inochi Amaoto <inochiama@...look.com>, linux-kernel@...r.kernel.org,
Inochi Amaoto <inochiama@...il.com>,
Samuel Holland <samuel.holland@...ive.com>, sophgo@...ts.linux.dev,
Paul Walmsley <paul.walmsley@...ive.com>,
Conor Dooley <conor+dt@...nel.org>, Alexandre Ghiti <alex@...ti.fr>,
Palmer Dabbelt <palmer@...belt.com>,
Palmer Dabbelt <palmer@...ive.com>, Conor Dooley <conor@...nel.org>
Subject: Re: [PATCH v3 05/13] dt-bindings: interrupt-controller: Add Anlogic
DR1V90 ACLINT MSWI
On Tue, 21 Oct 2025 17:41:40 +0800, Junhui Liu wrote:
> Add MSWI support for Anlogic DR1V90 SoC, which uses Nuclei UX900 with a
> TIMER unit compliant with the ACLINT specification.
>
> Signed-off-by: Junhui Liu <junhui.liu@...moral.tech>
> ---
> .../interrupt-controller/thead,c900-aclint-mswi.yaml | 17 +++++++++++------
> 1 file changed, 11 insertions(+), 6 deletions(-)
>
Acked-by: Rob Herring (Arm) <robh@...nel.org>
Powered by blists - more mailing lists