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Message-ID: <2b4cd5a6-98f8-4ec6-bdac-c6c7dae84049@rivosinc.com>
Date: Mon, 27 Oct 2025 14:29:29 +0100
From: Clément Léger <cleger@...osinc.com>
To: Xu Lu <luxu.kernel@...edance.com>
Cc: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
Himanshu Chauhan <hchauhan@...tanamicro.com>,
Anup Patel <apatel@...tanamicro.com>, Atish Patra <atishp@...shpatra.org>,
Björn Töpel <bjorn@...osinc.com>,
Yunhui Cui <cuiyunhui@...edance.com>
Subject: Re: [External] [PATCH v7 2/5] riscv: add support for SBI Supervisor
Software Events extension
On 10/27/25 13:00, Xu Lu wrote:
>> +void do_sse(struct sse_event_arch_data *arch_evt, struct pt_regs *regs)
>> +{
>> + nmi_enter();
>> +
>> + /* Retrieve missing GPRs from SBI */
>> + sbi_ecall(SBI_EXT_SSE, SBI_SSE_EVENT_ATTR_READ, arch_evt->evt_id,
>> + SBI_SSE_ATTR_INTERRUPTED_A6,
>> + (SBI_SSE_ATTR_INTERRUPTED_A7 - SBI_SSE_ATTR_INTERRUPTED_A6) + 1,
>> + arch_evt->interrupted_phys, 0, 0);
>> +
>> + memcpy(®s->a6, &arch_evt->interrupted, sizeof(arch_evt->interrupted));
>> +
>> + sse_handle_event(arch_evt, regs);
>> +
>> + /*
>> + * The SSE delivery path does not uses the "standard" exception path
>> + * (see sse_entry.S) and does not process any pending signal/softirqs
>> + * due to being similar to a NMI.
>> + * Some drivers (PMU, RAS) enqueue pending work that needs to be handled
>> + * as soon as possible by bottom halves. For that purpose, set the SIP
>> + * software interrupt pending bit which will force a software interrupt
>> + * to be serviced once interrupts are reenabled in the interrupted
>> + * context if they were masked or directly if unmasked.
>> + */
>> + csr_set(CSR_IP, IE_SIE);
> IE_SIE may not always be enabled in CSR_IE(for example when we disable
> CONFIG_ACLINT_SSWI and use imsic for ipi). Maybe we should send ipi to
> the current cpu here.
Hi Xu,
Indeed, that's a good catch. Sending an IPI will be more generic.
Thanks,
Clément
>
> Best regards,
> Xu Lu
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