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Message-ID: <feba1845-5f2f-4716-950c-9abc7c4594a9@gmail.com>
Date: Mon, 27 Oct 2025 08:17:40 -0700
From: Laurentiu Mihalcea <laurentiumihalcea111@...il.com>
To: Peng Fan <peng.fan@....nxp.com>
Cc: Abel Vesa <abelvesa@...nel.org>, Peng Fan <peng.fan@....com>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd
 <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
 Fabio Estevam <festevam@...il.com>, Philipp Zabel <p.zabel@...gutronix.de>,
 Daniel Baluta <daniel.baluta@....com>, Shengjiu Wang
 <shengjiu.wang@....com>, linux-clk@...r.kernel.org, imx@...ts.linux.dev,
 devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org, Pengutronix Kernel Team <kernel@...gutronix.de>
Subject: Re: [PATCH v2 2/8] dt-bindings: clock: document 8ULP's SIM LPAV
On 10/22/2025 7:08 AM, Peng Fan wrote:
> Hi Laurentiu,
>
> On Fri, Oct 17, 2025 at 04:20:19AM -0700, Laurentiu Mihalcea wrote:
>> From: Laurentiu Mihalcea <laurentiu.mihalcea@....com>
>>
>> Add documentation for i.MX8ULP's SIM LPAV module.
>>
>> Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@....com>
>> ---
>> +description:
>> +  The i.MX8ULP LPAV subsystem contains a block control module known as
>> +  SIM LPAV, which offers functionalities such as clock gating or reset
>> +  line assertion/de-assertion.
>> +
>> +properties:
>> +  compatible:
>> +    const: fsl,imx8ulp-sim-lpav
> This block also contains QoS registers, General purpose registers, HIFI
> general purpose registers, and others.
>
> I am not sure whether need to add a syscon fallback here. dt maintainer may
> help comment.
syscon programming model is NOT compatible with this programming model.
If you need access to other registers (not covered by reset/MUX/clock APIs), you're going to have to either go
through a subsystem API or manually create a device link between SIM LPAV and your consumer and then use
something like dev_get_regmap().
Either way, you need to make sure that you're using the same lock for register access.
as for the interconnect QoS-related stuff: can't really comment on this as I haven't worked
with it, nor do I have an use case for it ATM. However, the binding does need to be complete so
suggestions in this regard would be much appreciated.
>
> Regards,
> Peng
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