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Message-ID: <20251027000537.GM13023@pendragon.ideasonboard.com>
Date: Mon, 27 Oct 2025 02:05:37 +0200
From: Laurent Pinchart <laurent.pinchart@...asonboard.com>
To: Guoniu Zhou <guoniu.zhou@....nxp.com>
Cc: Rui Miguel Silva <rmfrfs@...il.com>,
Martin Kepplinger <martink@...teo.de>,
Purism Kernel Team <kernel@...i.sm>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
Philipp Zabel <p.zabel@...gutronix.de>, Frank Li <Frank.Li@....com>,
linux-media@...r.kernel.org, devicetree@...r.kernel.org,
imx@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, Guoniu Zhou <guoniu.zhou@....com>,
Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [PATCH v7 1/5] media: dt-bindings: nxp,imx8mq-mipi-csi2: Add
i.MX8ULP compatible string
Hi Guoniu,
On Thu, Oct 23, 2025 at 05:19:42PM +0800, Guoniu Zhou wrote:
> From: Guoniu Zhou <guoniu.zhou@....com>
>
> The CSI-2 receiver in the i.MX8ULP is almost identical to the version
> present in the i.MX8QXP/QM, but i.MX8ULP CSI-2 controller needs pclk
> clock as the input clock for its APB interface of Control and Status
> register(CSR). So add compatible string fsl,imx8ulp-mipi-csi2 and
> increase maxItems of Clocks (clock-names) to 4 from 3. And keep the
> same restriction for existing compatible.
>
> Reviewed-by: Frank Li <Frank.Li@....com>
> Acked-by: Conor Dooley <conor.dooley@...rochip.com>
> Signed-off-by: Guoniu Zhou <guoniu.zhou@....com>
> ---
> .../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 41 ++++++++++++++++++++--
> 1 file changed, 39 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> index 3389bab266a9adbda313c8ad795b998641df12f3..da3978da1cab75292ada3f24837443f7f4ab6418 100644
> --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> @@ -20,6 +20,7 @@ properties:
> - enum:
> - fsl,imx8mq-mipi-csi2
> - fsl,imx8qxp-mipi-csi2
> + - fsl,imx8ulp-mipi-csi2
> - items:
> - const: fsl,imx8qm-mipi-csi2
> - const: fsl,imx8qxp-mipi-csi2
> @@ -39,12 +40,16 @@ properties:
> clock that the RX DPHY receives.
> - description: ui is the pixel clock (phy_ref up to 333Mhz).
> See the reference manual for details.
> + - description: pclk is clock for csr APB interface.
> + minItems: 3
>
> clock-names:
> items:
> - const: core
> - const: esc
> - const: ui
> + - const: pclk
> + minItems: 3
>
> power-domains:
> maxItems: 1
> @@ -130,19 +135,51 @@ allOf:
> compatible:
> contains:
> enum:
> - - fsl,imx8qxp-mipi-csi2
> + - fsl,imx8ulp-mipi-csi2
> + then:
> + properties:
> + reg:
> + minItems: 2
> + resets:
> + minItems: 2
> + maxItems: 2
> + clocks:
> + minItems: 4
> + clock-names:
> + minItems: 4
Do we need the clock-names constraint ? The DT schemas will enforce that
clocks and clock-names always have the same number of elements.
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: fsl,imx8qxp-mipi-csi2
> then:
> properties:
> reg:
> minItems: 2
> resets:
> maxItems: 1
> - else:
> + clocks:
> + maxItems: 3
> + clock-names:
> + maxItems: 3
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx8mq-mipi-csi2
> + then:
> properties:
> reg:
> maxItems: 1
> resets:
> minItems: 3
> + clocks:
> + maxItems: 3
> + clock-names:
> + maxItems: 3
> required:
> - fsl,mipi-phy-gpr
>
Could you please sort those conditional blocks by alphabetical order of
the compatible strings ?
--
Regards,
Laurent Pinchart
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