linux-kernel - Re: [PATCH v2 0/6] clk/reset: anlogic: add support for DR1V90 SoC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <A61F456C6F5290B8+aP7O37HtuMNAYHpi@kernel.org>
Date: Mon, 27 Oct 2025 09:46:07 +0800
From: Troy Mitchell <troy.mitchell@...ux.spacemit.com>
To: Junhui Liu <junhui.liu@...moral.tech>,
	Troy Mitchell <troy.mitchell@...ux.spacemit.com>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Philipp Zabel <p.zabel@...gutronix.de>,
	Paul Walmsley <pjw@...nel.org>, Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>
Cc: linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
	Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [PATCH v2 0/6] clk/reset: anlogic: add support for DR1V90 SoC

On Mon, Oct 27, 2025 at 09:39:09AM +0800, Junhui Liu wrote:
> Hi Troy,
> 
> On 10/27/25 9:22 AM, Troy Mitchell wrote:
> > On Sun, Oct 26, 2025 at 10:00:40PM +0800, Junhui Liu wrote:
> > > This adds Clock and Reset Unit (CRU) support for the Anlogic DR1V90 SoC,
> > > as well as corresponding dts bindings and dts integration.
> > > 
> > > The CRU driver framework is built around the clock controller as the
> > > primary device, with the reset controller implemented as an auxiliary
> > > device. The clock part refers to the vendor's code [1] to determine the
> > > structure of the clock tree.
> > > 
> > > The Anlogic DR1 series includes not only the DR1V90 (based on the Nuclei
> > > UX900 RISC-V core), but also the DR1M90 (based on the Cortex-A35 ARM64
> > > core). Most of the clock tree and CRU design can be shared between them.
> > > This series only adds CRU support for DR1V90. Nevertheless, the driver
> > > is structured to make future extension to other DR1 variants like
> > > DR1M90.
> > > 
> > > This depends on the basic dt series for DR1V90 SoC [2].
> > > 
> > > Link: https://gitee.com/anlogic/linux/blob/anlogic-6.1.54/drivers/clk/anlogic/anl_dr1x90_crp.c [1]
> > > Link: https://lore.kernel.org/all/20251021-dr1v90-basic-dt-v3-0-5478db4f664a@pigmoral.tech/ [2]
> > > ---
> > Do we really need a cover-letter? Since you only have one patch, Is it
> > better to put the above information below the --- line in the actual patch?
> 
> Yes, we do need a cover letter since there are 6 patches in this series.
> I think the b4 tool only added you to the To list in patch 0 and 1 because
> you gave a Reviewed-by to patch 1 in v1. You can check the full patch
> series from the mailing list [1]. Thanks.
> 
> [1] https://lore.kernel.org/all/20251026-dr1v90-cru-v2-0-43b67acd6ddd@pigmoral.tech
OOPS!I missed that...
Thanks for your link.

                - Troy