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Message-ID: <20251027095825.181161-5-jacky_chou@aspeedtech.com>
Date: Mon, 27 Oct 2025 17:58:20 +0800
From: Jacky Chou <jacky_chou@...eedtech.com>
To: <lpieralisi@...nel.org>, <kwilczynski@...nel.org>, <mani@...nel.org>,
<robh@...nel.org>, <bhelgaas@...gle.com>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, <joel@....id.au>, <andrew@...econstruct.com.au>,
<vkoul@...nel.org>, <kishon@...nel.org>, <linus.walleij@...aro.org>,
<p.zabel@...gutronix.de>, <linux-aspeed@...ts.ozlabs.org>,
<linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<linux-phy@...ts.infradead.org>, <openbmc@...ts.ozlabs.org>,
<linux-gpio@...r.kernel.org>
CC: <jacky_chou@...eedtech.com>
Subject: [PATCH v4 4/9] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST#
Add pinctrl support for PCIe RC PERST#.
Signed-off-by: Jacky Chou <jacky_chou@...eedtech.com>
---
arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi
index e87c4b58994a..d46f2047135c 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi
+++ b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi
@@ -2,6 +2,11 @@
// Copyright 2019 IBM Corp.
&pinctrl {
+ pinctrl_pcierc1_default: pcierc1-default {
+ function = "PCIERC1";
+ groups = "PCIERC1";
+ };
+
pinctrl_adc0_default: adc0_default {
function = "ADC0";
groups = "ADC0";
--
2.34.1
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