linux-kernel - RE: [PATCH 01/10] clk: renesas: r9a09g077: add TSU module clock

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Message-ID:
 <TYYPR01MB105128801D5B38F5D016E589485FCA@TYYPR01MB10512.jpnprd01.prod.outlook.com>
Date: Mon, 27 Oct 2025 10:54:06 +0000
From: Cosmin-Gabriel Tanislav <cosmin-gabriel.tanislav.xa@...esas.com>
To: geert <geert@...ux-m68k.org>
CC: John Madieu <john.madieu.xa@...renesas.com>, "Rafael J . Wysocki"
	<rafael@...nel.org>, Daniel Lezcano <daniel.lezcano@...aro.org>, Zhang Rui
	<rui.zhang@...el.com>, Lukasz Luba <lukasz.luba@....com>, Rob Herring
	<robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
	<conor+dt@...nel.org>, Geert Uytterhoeven <geert+renesas@...der.be>,
	magnus.damm <magnus.damm@...il.com>, Michael Turquette
	<mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Philipp Zabel
	<p.zabel@...gutronix.de>, "linux-pm@...r.kernel.org"
	<linux-pm@...r.kernel.org>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "linux-renesas-soc@...r.kernel.org"
	<linux-renesas-soc@...r.kernel.org>, "linux-clk@...r.kernel.org"
	<linux-clk@...r.kernel.org>
Subject: RE: [PATCH 01/10] clk: renesas: r9a09g077: add TSU module clock



> -----Original Message-----
> From: Geert Uytterhoeven <geert@...ux-m68k.org>
> Sent: Monday, October 27, 2025 12:45 PM
> To: Cosmin-Gabriel Tanislav <cosmin-gabriel.tanislav.xa@...esas.com>
> Cc: John Madieu <john.madieu.xa@...renesas.com>; Rafael J . Wysocki <rafael@...nel.org>; Daniel Lezcano
> <daniel.lezcano@...aro.org>; Zhang Rui <rui.zhang@...el.com>; Lukasz Luba <lukasz.luba@....com>; Rob
> Herring <robh@...nel.org>; Krzysztof Kozlowski <krzk+dt@...nel.org>; Conor Dooley
> <conor+dt@...nel.org>; Geert Uytterhoeven <geert+renesas@...der.be>; magnus.damm
> <magnus.damm@...il.com>; Michael Turquette <mturquette@...libre.com>; Stephen Boyd <sboyd@...nel.org>;
> Philipp Zabel <p.zabel@...gutronix.de>; linux-pm@...r.kernel.org; devicetree@...r.kernel.org; linux-
> kernel@...r.kernel.org; linux-renesas-soc@...r.kernel.org; linux-clk@...r.kernel.org
> Subject: Re: [PATCH 01/10] clk: renesas: r9a09g077: add TSU module clock
> 
> On Thu, 23 Oct 2025 at 10:20, Cosmin Tanislav
> <cosmin-gabriel.tanislav.xa@...esas.com> wrote:
> > The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a TSU
> > peripheral with controlled by a module clock.
> >
> > The TSU module clock is enabled in register MSTPCRG (0x30c), at bit 7,
> 
> MSTPCRD
> 
> I will fix that while applying.
> 

Thank you for spotting this, I double checked and indeed it's
MSTPCRD not MSTPCRG.

> > resulting in a (0x30c - 0x300) / 4 * 100 + 7 = 307 index.
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds