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Message-ID: <aP9y3nK0FlgINa0o@hovoldconsulting.com>
Date: Mon, 27 Oct 2025 14:25:50 +0100
From: Johan Hovold <johan@...nel.org>
To: Bjorn Helgaas <helgaas@...nel.org>
Cc: linux-pci@...r.kernel.org,
Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>,
Krzysztof WilczyĆski <kwilczynski@...nel.org>,
Frank Li <Frank.li@....com>, Shawn Lin <shawn.lin@...k-chips.com>,
Rob Herring <robh@...nel.org>,
"David E . Box" <david.e.box@...ux.intel.com>,
Kai-Heng Feng <kai.heng.feng@...onical.com>,
"Rafael J . Wysocki" <rafael@...nel.org>,
Heiner Kallweit <hkallweit1@...il.com>,
Chia-Lin Kao <acelan.kao@...onical.com>,
Gustavo Pimentel <Gustavo.Pimentel@...opsys.com>,
Han Jingoo <jingoohan1@...il.com>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
Bartosz Golaszewski <brgl@...ev.pl>, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org, Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: [PATCH] Revert "PCI: qcom: Remove custom ASPM enablement code"
On Fri, Oct 24, 2025 at 04:04:57PM -0500, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <bhelgaas@...gle.com>
>
> This reverts commit a729c16646198872e345bf6c48dbe540ad8a9753.
>
> Prior to a729c1664619 ("PCI: qcom: Remove custom ASPM enablement code"),
> the qcom controller driver enabled ASPM, including L0s, L1, and L1 PM
> Substates, for all devices powered on at the time the controller driver
> enumerates them.
>
> ASPM was *not* enabled for devices powered on later by pwrctrl (unless the
> kernel was built with PCIEASPM_POWERSAVE or PCIEASPM_POWER_SUPERSAVE, or
> the user enabled ASPM via module parameter or sysfs).
>
> After f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for
> devicetree platforms"), the PCI core enabled all ASPM states for all
> devices whether powered on initially or by pwrctrl, so a729c1664619 was
> unnecessary and reverted.
>
> But f3ac2ff14834 was too aggressive and broke platforms that didn't support
> CLKREQ# or required device-specific configuration for L1 Substates, so
> df5192d9bb0e ("PCI/ASPM: Enable only L0s and L1 for devicetree platforms")
> enabled only L0s and L1.
>
> On Qualcomm platforms, this left L1 Substates disabled, which was a
> regression. Revert a729c1664619 so L1 Substates will be enabled on devices
> that are initially powered on. Devices powered on by pwrctrl will be
> addressed later.
>
> Fixes: df5192d9bb0e ("PCI/ASPM: Enable only L0s and L1 for devicetree platforms")
> Signed-off-by: Bjorn Helgaas <bhelgaas@...gle.com>
This indeed re-enables L1SS for the X13s NVMe:
Reported-by: Johan Hovold <johan@...nel.org>
Link: https://lore.kernel.org/lkml/aPuXZlaawFmmsLmX@hovoldconsulting.com/
Tested-by: Johan Hovold <johan@...nel.org>
Johan
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