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Message-ID:
<TY3PR01MB113462A9E19F5AF62DB26CA5E86FDA@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Tue, 28 Oct 2025 15:08:50 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: Hugo Villeneuve <hugo@...ovil.com>
CC: Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Jiri Slaby
<jirislaby@...nel.org>, Geert Uytterhoeven <geert+renesas@...der.be>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>, wsa+renesas
<wsa+renesas@...g-engineering.com>, Claudiu Beznea
<claudiu.beznea.uj@...renesas.com>, Nam Cao <namcao@...utronix.de>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-serial@...r.kernel.org" <linux-serial@...r.kernel.org>, biju.das.au
<biju.das.au@...il.com>, "linux-renesas-soc@...r.kernel.org"
<linux-renesas-soc@...r.kernel.org>
Subject: RE: [PATCH 12/19] serial: sh-sci: Add support for RZ/G3E RSCI clks
Hi Hugo,
Thanks for the feedback.
> -----Original Message-----
> From: Hugo Villeneuve <hugo@...ovil.com>
> Sent: 28 October 2025 14:51
> Subject: Re: [PATCH 12/19] serial: sh-sci: Add support for RZ/G3E RSCI clks
>
> Hi Biju,
>
> On Mon, 27 Oct 2025 15:45:59 +0000
> Biju Das <biju.das.jz@...renesas.com> wrote:
>
> > RZ/G3E RSCI has 5 module clocks. Add support for these clocks.
>
> In "[PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support", you mention that
> "...RZ/G3E has 6 clocks...", and here 5?
5 module clocks + 1 external clock = 6 clocks.
I just omitted external clock here as it is available on both G3E and T2H.
Cheers,
Biju
>
>
> > Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
> > ---
> > drivers/tty/serial/sh-sci-common.h | 3 +++
> > drivers/tty/serial/sh-sci.c | 14 ++++++++++++++
> > 2 files changed, 17 insertions(+)
> >
> > diff --git a/drivers/tty/serial/sh-sci-common.h
> > b/drivers/tty/serial/sh-sci-common.h
> > index ef1d94ae8b5c..f730ff9add60 100644
> > --- a/drivers/tty/serial/sh-sci-common.h
> > +++ b/drivers/tty/serial/sh-sci-common.h
> > @@ -17,6 +17,9 @@ enum SCI_CLKS {
> > SCI_SCK, /* Optional External Clock */
> > SCI_BRG_INT, /* Optional BRG Internal Clock Source */
> > SCI_SCIF_CLK, /* Optional BRG External Clock Source */
> > + SCI_FCK_DIV64, /* Optional Functional Clock frequency-divided by 64 */
> > + SCI_FCK_DIV16, /* Optional Functional Clock frequency-divided by 16 */
> > + SCI_FCK_DIV4, /* Optional Functional Clock frequency-divided by 4 */
>
> I see 6 clocks here?
>
> > SCI_NUM_CLKS
> > };
> >
> > diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> > index 5f5913410df9..d45bdda2b6c1 100644
> > --- a/drivers/tty/serial/sh-sci.c
> > +++ b/drivers/tty/serial/sh-sci.c
> > @@ -2994,6 +2994,9 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
> > [SCI_SCK] = "sck",
> > [SCI_BRG_INT] = "brg_int",
> > [SCI_SCIF_CLK] = "scif_clk",
> > + [SCI_FCK_DIV64] = "tclk_div64",
> > + [SCI_FCK_DIV16] = "tclk_div16",
> > + [SCI_FCK_DIV4] = "tclk_div4",
> > };
> > struct clk *clk;
> > unsigned int i;
> > @@ -3003,6 +3006,9 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
> > } else if (sci_port->type == SCI_PORT_RSCI) {
> > clk_names[SCI_FCK] = "operation";
> > clk_names[SCI_BRG_INT] = "bus";
> > + } else if (sci_port->type == RSCI_PORT_SCI || sci_port->type == RSCI_PORT_SCIF) {
> > + clk_names[SCI_FCK] = "tclk";
> > + clk_names[SCI_BRG_INT] = "bus";
> > }
> >
> > for (i = 0; i < SCI_NUM_CLKS; i++) { @@ -3018,6 +3024,14 @@ static
> > int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
> > name);
> > }
> >
> > + if (!clk && (sci_port->type == RSCI_PORT_SCI ||
> > + sci_port->type == RSCI_PORT_SCIF) &&
> > + (i == SCI_FCK || i == SCI_BRG_INT || i == SCI_FCK_DIV64 ||
> > + i == SCI_FCK_DIV16 || i == SCI_FCK_DIV4)) {
> > + return dev_err_probe(dev, -ENODEV, "failed to get %s\n",
> > + name);
> > + }
> > +
> > if (!clk && i == SCI_FCK) {
> > /*
> > * Not all SH platforms declare a clock lookup entry
> > --
> > 2.43.0
> >
> >
>
> --
> Hugo Villeneuve
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