linux-kernel - [PATCH v2 5/7] arm64: dts: qcom: msm8953: Add CCI nodes

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Message-Id: <20251028-msm8953-cci-v2-5-b5f9f7135326@lucaweiss.eu>
Date: Tue, 28 Oct 2025 17:40:50 +0100
From: Luca Weiss <luca@...aweiss.eu>
To: ~postmarketos/upstreaming@...ts.sr.ht, phone-devel@...r.kernel.org, 
 Loic Poulain <loic.poulain@....qualcomm.com>, 
 Robert Foss <rfoss@...nel.org>, Andi Shyti <andi.shyti@...nel.org>, 
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, Bartosz Golaszewski <brgl@...ev.pl>, 
 Bjorn Andersson <andersson@...nel.org>, 
 Konrad Dybcio <konradybcio@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-i2c@...r.kernel.org, 
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
 Luca Weiss <luca@...aweiss.eu>, 
 Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: [PATCH v2 5/7] arm64: dts: qcom: msm8953: Add CCI nodes

Add the nodes for the camera I2C bus on the MSM8953 SoC.

Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Signed-off-by: Luca Weiss <luca@...aweiss.eu>
---
 arch/arm64/boot/dts/qcom/msm8953.dtsi | 57 +++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index 7884a3ed8aef..753167c3f861 100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -753,6 +753,20 @@ i2c_6_sleep: i2c-6-sleep-state {
 				bias-disable;
 			};
 
+			cci0_default: cci0-default-state {
+				pins = "gpio29", "gpio30";
+				function = "cci_i2c";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			cci1_default: cci1-default-state {
+				pins = "gpio31", "gpio32";
+				function = "cci_i2c";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
 			wcnss_pin_a: wcnss-active-state {
 				wcss-wlan2-pins {
 					pins = "gpio76";
@@ -1200,6 +1214,49 @@ mdss_dsi1_phy: phy@...6400 {
 			};
 		};
 
+		cci: cci@...c000 {
+			compatible = "qcom,msm8953-cci";
+			reg = <0x1b0c000 0x4000>;
+
+			interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
+
+			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+				 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
+				 <&gcc GCC_CAMSS_CCI_CLK>,
+				 <&gcc GCC_CAMSS_AHB_CLK>;
+			clock-names = "camss_top_ahb",
+				      "cci_ahb",
+				      "cci",
+				      "camss_ahb";
+
+			assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
+					  <&gcc GCC_CAMSS_CCI_CLK>;
+			assigned-clock-rates = <80000000>,
+					       <19200000>;
+
+			pinctrl-0 = <&cci0_default &cci1_default>;
+			pinctrl-names = "default";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+
+			cci_i2c0: i2c-bus@0 {
+				reg = <0>;
+				clock-frequency = <400000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			cci_i2c1: i2c-bus@1 {
+				reg = <1>;
+				clock-frequency = <400000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
 		gpu: gpu@...0000 {
 			compatible = "qcom,adreno-506.0", "qcom,adreno";
 			reg = <0x01c00000 0x40000>;

-- 
2.51.2