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Message-ID: <20251028175458.1037397-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Tue, 28 Oct 2025 17:54:58 +0000
From: Prabhakar <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-renesas-soc@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH v2 5/5] arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Enable Ethernet support on the RZ/T2H and RZ/N2H EVKs.
Configure the MIIC converter in mode 0x6:
Port 0 <-> ETHSW Port 0
Port 1 <-> ETHSW Port 1
Port 2 <-> GMAC2
Port 3 <-> GMAC1
Enable the ETHSS, GMAC1 and GMAC2 nodes. ETHSW support will be added
once the switch driver is available.
Configure the MIIC converters to map ports according to the selected
switching mode, with converters 0 and 1 mapped to switch ports and
converters 2 and 3 mapped to GMAC ports.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
v1->v2 changes:
- Dropped *skew-psec properties which are not needed for
VSC8541 PHYs.
---
.../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 70 ++++++++++++++++
.../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 79 +++++++++++++++++++
.../dts/renesas/rzt2h-n2h-evk-common.dtsi | 70 ++++++++++++++++
3 files changed, 219 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
index 799c58afd6fe..33cbf74933de 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
@@ -149,7 +149,77 @@ &i2c1 {
status = "okay";
};
+&phy2 {
+ /*
+ * PHY2 Reset Configuration:
+ *
+ * SW6[1] = OFF; SW6[2] = ON; SW6[3] = OFF;
+ * P17_5 is used as GMAC_RESETOUT2#
+ */
+ reset-gpios = <&pinctrl RZT2H_GPIO(17, 5) GPIO_ACTIVE_LOW>;
+};
+
+&phy3 {
+ reset-gpios = <&pinctrl RZT2H_GPIO(32, 3) GPIO_ACTIVE_LOW>;
+};
+
&pinctrl {
+ /*
+ * ETH2 Pin Configuration:
+ *
+ * SW2[6] = OFF: MDC and MDIO of Ethernet port 2 are connected to GMAC2
+ * SW2[7] = ON: Pins P29_1-P29_7, P30_0-P30_4, and P31_2-P31_5 are used for Ethernet port 2
+ */
+ eth2_pins: eth2-pins {
+ pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
+ <RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD[0] */
+ <RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD[1] */
+ <RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD[2] */
+ <RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD[3] */
+ <RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
+ <RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
+ <RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD[0] */
+ <RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD[1] */
+ <RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD[2] */
+ <RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD[3] */
+ <RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
+ <RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
+ <RZT2H_PORT_PINMUX(31, 3, 0xf)>, /* ETH2_RXER */
+ <RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
+ <RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
+ <RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* ETH2_MDC */
+ <RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* ETH2_MDIO */
+ <RZT2H_PORT_PINMUX(31, 0, 0x02)>; /* ETH2_REFCLK */
+ };
+
+ /*
+ * ETH3 Pin Configuration:
+ *
+ * SW2[8] = ON, P27_2, P33_2-P33_7, P34_0-P34_5, P34_7 and P35_0-P35_5
+ * are used for Ethernet port 3
+ */
+ eth3_pins: eth3-pins {
+ pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
+ <RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD[0] */
+ <RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD[1] */
+ <RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD[2] */
+ <RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD[3] */
+ <RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
+ <RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
+ <RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD[0] */
+ <RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD[1] */
+ <RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD[2] */
+ <RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD[3] */
+ <RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
+ <RZT2H_PORT_PINMUX(34, 7, 0xf)>, /* ETH3_TXER */
+ <RZT2H_PORT_PINMUX(35, 0, 0xf)>, /* ETH3_RXER */
+ <RZT2H_PORT_PINMUX(35, 1, 0xf)>, /* ETH3_CRS */
+ <RZT2H_PORT_PINMUX(35, 2, 0xf)>, /* ETH3_COL */
+ <RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* ETH3_MDC */
+ <RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* ETH3_MDIO */
+ <RZT2H_PORT_PINMUX(34, 6, 0x02)>; /* ETH3_REFCLK */
+ };
+
/*
* I2C0 Pin Configuration:
* ------------------------
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
index d698b6368ee7..7ebc89bafaf1 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
@@ -186,7 +186,86 @@ &i2c1 {
status = "okay";
};
+&phy2 {
+ /*
+ * PHY2 Reset Configuration:
+ *
+ * DSW8[1] = ON; DSW8[2] = OFF
+ * DSW12[7] = OFF; DSW12[8] = ON
+ * P03_1 is used as GMAC_RESETOUT2#
+ */
+ reset-gpios = <&pinctrl RZT2H_GPIO(3, 1) GPIO_ACTIVE_LOW>;
+};
+
+&phy3 {
+ /*
+ * PHY3 Reset Configuration:
+ *
+ * DSW12[5] = OFF; DSW12[6] = ON
+ * P03_2 is used as GMAC_RESETOUT3#
+ */
+ reset-gpios = <&pinctrl RZT2H_GPIO(3, 2) GPIO_ACTIVE_LOW>;
+};
+
&pinctrl {
+ /*
+ * ETH2 Pin Configuration:
+ *
+ * DSW5[6] = OFF, P21_4-P21_5 are used for Ethernet port 2
+ * DSW5[7] = ON, P29_1-P29_7, P30_0-P30_4, P30_7, P31_2, P31_4
+ * and P31_5 are used for Ethernet port 2
+ */
+ eth2_pins: eth2-pins {
+ pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
+ <RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD[0] */
+ <RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD[1] */
+ <RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD[2] */
+ <RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD[3] */
+ <RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
+ <RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
+ <RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD[0] */
+ <RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD[1] */
+ <RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD[2] */
+ <RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD[3] */
+ <RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
+ <RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
+ <RZT2H_PORT_PINMUX(31, 3, 0xf)>, /* ETH2_RXER */
+ <RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
+ <RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
+ <RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* ETH2_MDC */
+ <RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* ETH2_MDIO */
+ <RZT2H_PORT_PINMUX(31, 0, 0x02)>; /* ETH2_REFCLK */
+
+ };
+
+ /*
+ * ETH3 Pin Configuration:
+ *
+ * DSW5[8] = ON, P00_0-P00_2, P33_2-P33_7, P34_0-P34_6, are used for Ethernet port 3
+ * DSW12[1] = OFF;DSW12[2] = ON, P00_3 is used for Ethernet port 3
+ */
+ eth3_pins: eth3-pins {
+ pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
+ <RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD[0] */
+ <RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD[1] */
+ <RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD[2] */
+ <RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD[3] */
+ <RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
+ <RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
+ <RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD[0] */
+ <RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD[1] */
+ <RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD[2] */
+ <RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD[3] */
+ <RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
+ <RZT2H_PORT_PINMUX(0, 0, 0xf)>, /* ETH3_TXER */
+ <RZT2H_PORT_PINMUX(0, 1, 0xf)>, /* ETH3_RXER */
+ <RZT2H_PORT_PINMUX(0, 2, 0xf)>, /* ETH3_CRS */
+ <RZT2H_PORT_PINMUX(0, 3, 0xf)>, /* ETH3_COL */
+ <RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* ETH3_MDC */
+ <RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* ETH3_MDIO */
+ <RZT2H_PORT_PINMUX(34, 6, 0x02)>; /* ETH3_REFCLK */
+ };
+
/*
* I2C0 Pin Configuration:
* ------------------------
diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
index 924a38c6cb0f..c608d97586ff 100644
--- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -7,10 +7,14 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/mscc-phy-vsc8531.h>
+#include <dt-bindings/net/renesas,r9a09g077-pcs-miic.h>
#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
/ {
aliases {
+ ethernet0 = &gmac1;
+ ethernet1 = &gmac2;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhi0;
@@ -70,10 +74,34 @@ &ehci {
status = "okay";
};
+ðss {
+ status = "okay";
+
+ renesas,miic-switch-portin = <ETHSS_GMAC0_PORT>;
+};
+
&extal_clk {
clock-frequency = <25000000>;
};
+&gmac1 {
+ pinctrl-0 = <ð3_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&phy3>;
+ phy-mode = "rgmii-id";
+ pcs-handle = <&mii_conv3>;
+ status = "okay";
+};
+
+&gmac2 {
+ pinctrl-0 = <ð2_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&phy2>;
+ phy-mode = "rgmii-id";
+ pcs-handle = <&mii_conv2>;
+ status = "okay";
+};
+
&hsusb {
dr_mode = "otg";
status = "okay";
@@ -87,6 +115,48 @@ eeprom: eeprom@50 {
};
};
+&mdio1 {
+ phy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ vsc8531,led-0-mode = <VSC8531_LINK_ACTIVITY>;
+ vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
+ reset-assert-us = <2000>;
+ reset-deassert-us = <15000>;
+ };
+};
+
+&mdio2 {
+ phy2: ethernet-phy@2 {
+ compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ vsc8531,led-0-mode = <VSC8531_LINK_ACTIVITY>;
+ vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
+ reset-assert-us = <2000>;
+ reset-deassert-us = <15000>;
+ };
+};
+
+&mii_conv0 {
+ renesas,miic-input = <ETHSS_ETHSW_PORT0>;
+ status = "okay";
+};
+
+&mii_conv1 {
+ renesas,miic-input = <ETHSS_ETHSW_PORT1>;
+ status = "okay";
+};
+
+&mii_conv2 {
+ renesas,miic-input = <ETHSS_GMAC2_PORT>;
+ status = "okay";
+};
+
+&mii_conv3 {
+ renesas,miic-input = <ETHSS_GMAC1_PORT>;
+ status = "okay";
+};
+
&ohci {
dr_mode = "otg";
status = "okay";
--
2.43.0
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