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Message-ID: <20251028204832.GN15521@sventech.com>
Date: Tue, 28 Oct 2025 13:48:32 -0700
From: Johannes Erdfelt <johannes@...felt.com>
To: Alex Elder <elder@...cstar.com>
Cc: robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
bhelgaas@...gle.com, lpieralisi@...nel.org, kwilczynski@...nel.org,
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dlan@...too.org, guodong@...cstar.com, pjw@...nel.org,
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qiang.yu@....qualcomm.com, namcao@...utronix.de,
thippeswamy.havalige@....com, inochiama@...il.com,
devicetree@...r.kernel.org, linux-pci@...r.kernel.org,
linux-phy@...ts.infradead.org, spacemit@...ts.linux.dev,
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Subject: Re: [PATCH v2 0/7] Introduce SpacemiT K1 PCIe phy and host controller
On Tue, Oct 28, 2025, Alex Elder <elder@...cstar.com> wrote:
> On 10/28/25 1:42 PM, Johannes Erdfelt wrote:
> > I have been testing this patchset recently as well, but on an Orange Pi
> > RV2 board instead (and an extra RV2 specific patch to enable power to
> > the M.2 slot).
> >
> > I ran into the same symptoms you had ("QID 0 timeout" after about 60
> > seconds). However, I'm using an Intel 600p. I can confirm my NVME drive
> > seems to work fine with the "pcie_aspm=off" workaround as well.
>
> I don't see this problem, and haven't tried to reproduce it yet.
>
> Mani told me I needed to add these lines to ensure the "runtime
> PM hierarchy of PCIe chain" won't be "broken":
>
> pm_runtime_set_active()
> pm_runtime_no_callbacks()
> devm_pm_runtime_enable()
>
> Just out of curiosity, could you try with those lines added
> just before these assignments in k1_pcie_probe()?
>
> k1->pci.dev = dev;
> k1->pci.ops = &k1_pcie_ops;
> dw_pcie_cap_set(&k1->pci, REQ_RES);
>
> I doubt it will fix what you're seeing, but at the moment I'm
> working on something else.
Unfortunately there is no difference with the runtime PM hierarchy
additions.
JE
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