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Message-ID: <0a32fc1d-c6cb-4090-9ef3-777affe18b87@nvidia.com>
Date: Tue, 28 Oct 2025 11:14:22 +0530
From: Kartik Rajput <kkartik@...dia.com>
To: Jon Hunter <jonathanh@...dia.com>, akhilrajeev@...dia.com,
andi.shyti@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, thierry.reding@...il.com, ldewangan@...dia.com,
digetx@...il.com, smangipudi@...dia.com, linux-i2c@...r.kernel.org,
devicetree@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] i2c: tegra: Add support for Tegra410
On 24/10/25 20:47, Jon Hunter wrote:
>
>
> On 01/10/2025 16:36, Kartik Rajput wrote:
>> Add support for the Tegra410 SoC, which has 4 I2C controllers. The
>> controllers are feature-equivalent to Tegra264; only the register
>> offsets differ.
>>
>> Signed-off-by: Kartik Rajput <kkartik@...dia.com>
>> ---
>> drivers/i2c/busses/i2c-tegra.c | 64 ++++++++++++++++++++++++++++++++++
>> 1 file changed, 64 insertions(+)
>>
>> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
>> index 1e26d67cbd30..bc9f60b69020 100644
>> --- a/drivers/i2c/busses/i2c-tegra.c
>> +++ b/drivers/i2c/busses/i2c-tegra.c
>> @@ -262,6 +262,38 @@ static const struct tegra_i2c_regs tegra20_i2c_regs_vi = {
>> .dvc_status = 0x00c,
>> };
>> +static const struct tegra_i2c_regs tegra410_i2c_regs = {
>> + .cnfg = 0x000,
>> + .status = 0x01c,
>> + .sl_cnfg = 0x020,
>> + .sl_addr1 = 0x02c,
>> + .sl_addr2 = 0x030,
>> + .tlow_sext = 0x034,
>> + .tx_fifo = 0x054,
>> + .rx_fifo = 0x058,
>> + .packet_transfer_status = 0x05c,
>> + .fifo_control = 0x060,
>> + .fifo_status = 0x064,
>> + .int_mask = 0x068,
>> + .int_status = 0x06c,
>> + .clk_divisor = 0x070,
>> + .bus_clear_cnfg = 0x088,
>> + .bus_clear_status = 0x08c,
>> + .config_load = 0x090,
>> + .clken_override = 0x094,
>> + .interface_timing_0 = 0x098,
>> + .interface_timing_1 = 0x09c,
>> + .hs_interface_timing_0 = 0x0a0,
>> + .hs_interface_timing_1 = 0x0a4,
>> + .master_reset_cntrl = 0x0ac,
>> + .mst_fifo_control = 0x0b8,
>> + .mst_fifo_status = 0x0bc,
>> + .sw_mutex = 0x0f0,
>> + .dvc_ctrl_reg1 = 0x000,
>> + .dvc_ctrl_reg3 = 0x008,
>> + .dvc_status = 0x00c,
>
> We define dvc regs here but ...
>
Ack, I will remove dvc related regs from here.
>> +};
>> +
>> /*
>> * msg_end_type: The bus control which needs to be sent at end of transfer.
>> * @MSG_END_STOP: Send stop pulse.
>> @@ -2020,6 +2052,37 @@ static const struct tegra_i2c_hw_feature tegra264_i2c_hw = {
>> .regs = &tegra20_i2c_regs,
>> };
>> +static const struct tegra_i2c_hw_feature tegra410_i2c_hw = {
>> + .has_continue_xfer_support = true,
>> + .has_per_pkt_xfer_complete_irq = true,
>> + .clk_divisor_hs_mode = 1,
>> + .clk_divisor_std_mode = 0x1d,
>> + .clk_divisor_fast_mode = 0x15,
>> + .clk_divisor_fast_plus_mode = 0x8,
>> + .has_config_load_reg = true,
>> + .has_multi_master_mode = true,
>> + .has_slcg_override_reg = true,
>> + .has_mst_fifo = true,
>> + .quirks = &tegra194_i2c_quirks,
>> + .supports_bus_clear = true,
>> + .has_apb_dma = false,
>> + .tlow_std_mode = 0x8,
>> + .thigh_std_mode = 0x7,
>> + .tlow_fast_fastplus_mode = 0x2,
>> + .thigh_fast_fastplus_mode = 0x2,
>> + .tlow_hs_mode = 0x4,
>> + .thigh_hs_mode = 0x2,
>> + .setup_hold_time_std_mode = 0x08080808,
>> + .setup_hold_time_fast_fast_plus_mode = 0x02020202,
>> + .setup_hold_time_hs_mode = 0x090909,
>> + .has_interface_timing_reg = true,
>> + .has_hs_mode_support = true,
>> + .has_mutex = true,
>> + .is_dvc = false,
>
> dvc is not supported.
>
>> + .is_vi = false,
>> + .regs = &tegra410_i2c_regs,
>> +};
>> +
>> static const struct of_device_id tegra_i2c_of_match[] = {
>> { .compatible = "nvidia,tegra264-i2c", .data = &tegra264_i2c_hw, },
>> { .compatible = "nvidia,tegra256-i2c", .data = &tegra256_i2c_hw, },
>> @@ -2330,6 +2393,7 @@ static const struct acpi_device_id tegra_i2c_acpi_match[] = {
>> {.id = "NVDA0101", .driver_data = (kernel_ulong_t)&tegra210_i2c_hw},
>> {.id = "NVDA0201", .driver_data = (kernel_ulong_t)&tegra186_i2c_hw},
>> {.id = "NVDA0301", .driver_data = (kernel_ulong_t)&tegra194_i2c_hw},
>> + {.id = "NVDA2017", .driver_data = (kernel_ulong_t)&tegra410_i2c_hw},
>> { }
>> };
>> MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match);
>
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