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Message-Id: <20251027-cpu_cluster_component_pm-v1-12-31355ac588c2@oss.qualcomm.com>
Date: Mon, 27 Oct 2025 23:28:14 -0700
From: Yuanfang Zhang <yuanfang.zhang@....qualcomm.com>
To: Suzuki K Poulose <suzuki.poulose@....com>,
Mike Leach <mike.leach@...aro.org>,
James Clark <james.clark@...aro.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Leo Yan <leo.yan@...ux.dev>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>
Cc: kernel@....qualcomm.com, coresight@...ts.linaro.org,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
Yuanfang Zhang <yuanfang.zhang@....qualcomm.com>,
Jie Gan <jie.gan@....qualcomm.com>
Subject: [PATCH 12/12] arm64: dts: qcom: x1e80100: add Coresight nodes for
APSS debug block
Add below Coresight devices for APSS debug block:
-ETM
-TMC ETF
-Funnel
-Replicator
Signed-off-by: Jie Gan <jie.gan@....qualcomm.com>
Signed-off-by: Yuanfang Zhang <yuanfang.zhang@....qualcomm.com>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 885 +++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/x1p42100.dtsi | 12 +
2 files changed, 897 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index a9a7bb676c6f8ac48a2e443d28efdc8c9b5e52c0..9058ea8ce62c706667b931a8f4c2e7c666c6bcc4 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -6597,6 +6597,14 @@ funnel1_in2: endpoint {
};
};
+ port@4 {
+ reg = <4>;
+
+ funnel1_in4: endpoint {
+ remote-endpoint = <&apss_funnel_out>;
+ };
+ };
+
port@5 {
reg = <5>;
@@ -7887,6 +7895,883 @@ ddr_funnel1_out: endpoint {
};
};
+ apss_funnel: funnel@...80000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x12080000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ apss_funnel_in0: endpoint {
+ remote-endpoint = <&ncc0_etf_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ apss_funnel_in1: endpoint {
+ remote-endpoint = <&ncc1_etf_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ apss_funnel_in2: endpoint {
+ remote-endpoint = <&ncc2_etf_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ apss_funnel_out: endpoint {
+ remote-endpoint =
+ <&funnel1_in4>;
+ };
+ };
+ };
+ };
+
+ etm@...21000 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&ncc0_0_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm@...21000 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu1>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&ncc0_1_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm@...21000 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu2>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint = <&ncc0_2_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm@...21000 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu3>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint = <&ncc0_3_rep_in>;
+ };
+ };
+ };
+ };
+
+ funnel@...01000 {
+ compatible = "arm,coresight-cpu-funnel";
+ reg = <0x0 0x13401000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ ncc0_2_funnel_in2: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_2_funnel_out: endpoint {
+ remote-endpoint = <&ncc0_etf_in>;
+ };
+ };
+ };
+ };
+
+ tmc@...09000 {
+ compatible = "arm,coresight-cpu-tmc";
+ reg = <0x0 0x13409000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+
+ in-ports {
+ port {
+ ncc0_etf_in: endpoint {
+ remote-endpoint = <&ncc0_2_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_etf_out: endpoint {
+ remote-endpoint = <&apss_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ replicator@...90000 {
+ compatible = "arm,coresight-cpu-replicator";
+ reg = <0x0 0x13490000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+
+ in-ports {
+ port {
+ ncc0_0_rep_in: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_0_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ replicator@...a0000 {
+ compatible = "arm,coresight-cpu-replicator";
+ reg = <0x0 0x134a0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+
+ in-ports {
+ port {
+ ncc0_1_rep_in: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_1_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ replicator@...b0000 {
+ compatible = "arm,coresight-cpu-replicator";
+ reg = <0x0 0x134b0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+
+ in-ports {
+ port {
+ ncc0_2_rep_in: endpoint {
+ remote-endpoint = <&etm2_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_2_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ replicator@...c0000 {
+ compatible = "arm,coresight-cpu-replicator";
+ reg = <0x0 0x134c0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+
+ in-ports {
+ port {
+ ncc0_3_rep_in: endpoint {
+ remote-endpoint = <&etm3_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_3_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ funnel@...d0000 {
+ compatible = "arm,coresight-cpu-funnel";
+ reg = <0x0 0x134d0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ncc0_1_funnel_in0: endpoint {
+ remote-endpoint = <&ncc0_0_rep_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ncc0_1_funnel_in1: endpoint {
+ remote-endpoint = <&ncc0_1_rep_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ncc0_1_funnel_in2: endpoint {
+ remote-endpoint = <&ncc0_2_rep_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ ncc0_1_funnel_in3: endpoint {
+ remote-endpoint = <&ncc0_3_rep_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_1_funnel_out: endpoint {
+ remote-endpoint = <&ncc0_2_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ etm@...21000 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu4>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint = <&ncc1_0_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm@...21000 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu5>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint = <&ncc1_1_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm@...21000 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu6>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint = <&ncc1_2_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm@...21000 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu7>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint = <&ncc1_3_rep_in>;
+ };
+ };
+ };
+ };
+
+ funnel@...01000 {
+ compatible = "arm,coresight-cpu-funnel";
+ reg = <0x0 0x13901000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ ncc1_2_funnel_in2: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_2_funnel_out: endpoint {
+ remote-endpoint = <&ncc1_etf_in>;
+ };
+ };
+ };
+ };
+
+ tmc@...09000 {
+ compatible = "arm,coresight-cpu-tmc";
+ reg = <0x0 0x13909000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+
+ in-ports {
+ port {
+ ncc1_etf_in: endpoint {
+ remote-endpoint = <&ncc1_2_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_etf_out: endpoint {
+ remote-endpoint = <&apss_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ replicator@...90000 {
+ compatible = "arm,coresight-cpu-replicator";
+ reg = <0x0 0x13990000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+
+ in-ports {
+ port {
+ ncc1_0_rep_in: endpoint {
+ remote-endpoint = <&etm4_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_0_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ replicator@...a0000 {
+ compatible = "arm,coresight-cpu-replicator";
+ reg = <0x0 0x139a0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+
+ in-ports {
+ port {
+ ncc1_1_rep_in: endpoint {
+ remote-endpoint = <&etm5_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_1_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ replicator@...b0000 {
+ compatible = "arm,coresight-cpu-replicator";
+ reg = <0x0 0x139b0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+
+ in-ports {
+ port {
+ ncc1_2_rep_in: endpoint {
+ remote-endpoint = <&etm6_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_2_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ replicator@...c0000 {
+ compatible = "arm,coresight-cpu-replicator";
+ reg = <0x0 0x139c0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+
+ in-ports {
+ port {
+ ncc1_3_rep_in: endpoint {
+ remote-endpoint = <&etm7_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_3_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ funnel@...d0000 {
+ compatible = "arm,coresight-cpu-funnel";
+ reg = <0x0 0x139d0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ncc1_1_funnel_in0: endpoint {
+ remote-endpoint = <&ncc1_0_rep_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ncc1_1_funnel_in1: endpoint {
+ remote-endpoint = <&ncc1_1_rep_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ncc1_1_funnel_in2: endpoint {
+ remote-endpoint = <&ncc1_2_rep_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ ncc1_1_funnel_in3: endpoint {
+ remote-endpoint = <&ncc1_3_rep_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_1_funnel_out: endpoint {
+ remote-endpoint = <&ncc1_2_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ etm8: etm@...21000 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu8>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm8_out: endpoint {
+ remote-endpoint = <&ncc2_0_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm9: etm@...21000 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu9>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm9_out: endpoint {
+ remote-endpoint = <&ncc2_1_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm10: etm@...21000 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu10>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm10_out: endpoint {
+ remote-endpoint = <&ncc2_2_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm11: etm@...21000 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu11>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm11_out: endpoint {
+ remote-endpoint = <&ncc2_3_rep_in>;
+ };
+ };
+ };
+ };
+
+ cluster2_funnel_l2: funnel@...01000 {
+ compatible = "arm,coresight-cpu-funnel";
+ reg = <0x0 0x13e01000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ ncc2_2_funnel_in2: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_2_funnel_out: endpoint {
+ remote-endpoint = <&ncc2_etf_in>;
+ };
+ };
+ };
+ };
+
+ cluster2_etf: tmc@...09000 {
+ compatible = "arm,coresight-cpu-tmc";
+ reg = <0x0 0x13e09000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+
+ in-ports {
+ port {
+ ncc2_etf_in: endpoint {
+ remote-endpoint = <&ncc2_2_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_etf_out: endpoint {
+ remote-endpoint = <&apss_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_0: replicator@...90000 {
+ compatible = "arm,coresight-cpu-replicator";
+ reg = <0x0 0x13e90000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+
+ in-ports {
+ port {
+ ncc2_0_rep_in: endpoint {
+ remote-endpoint = <&etm8_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_0_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_1: replicator@...a0000 {
+ compatible = "arm,coresight-cpu-replicator";
+ reg = <0x0 0x13ea0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+
+ in-ports {
+ port {
+ ncc2_1_rep_in: endpoint {
+ remote-endpoint = <&etm9_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_1_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_2: replicator@...b0000 {
+ compatible = "arm,coresight-cpu-replicator";
+ reg = <0x0 0x13eb0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+
+ in-ports {
+ port {
+ ncc2_2_rep_in: endpoint {
+ remote-endpoint = <&etm10_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_2_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_3: replicator@...c0000 {
+ compatible = "arm,coresight-cpu-replicator";
+ reg = <0x0 0x13ec0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+
+ in-ports {
+ port {
+ ncc2_3_rep_in: endpoint {
+ remote-endpoint = <&etm11_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_3_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ cluster2_funnel_l1: funnel@...d0000 {
+ compatible = "arm,coresight-cpu-funnel";
+ reg = <0x0 0x13ed0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ncc2_1_funnel_in0: endpoint {
+ remote-endpoint = <&ncc2_0_rep_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ncc2_1_funnel_in1: endpoint {
+ remote-endpoint = <&ncc2_1_rep_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ncc2_1_funnel_in2: endpoint {
+ remote-endpoint = <&ncc2_2_rep_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ ncc2_1_funnel_in3: endpoint {
+ remote-endpoint = <&ncc2_3_rep_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_1_funnel_out: endpoint {
+ remote-endpoint = <&ncc2_2_funnel_in2>;
+ };
+ };
+ };
+ };
+
apps_smmu: iommu@...00000 {
compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
index 9af9e707f982fe45f62a9420b1e6baa1fef4d2fa..9b5fe04ed05cc33fe6d0a3535648d318f6cc3a80 100644
--- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
@@ -19,6 +19,18 @@
/delete-node/ &cpu_pd11;
/delete-node/ &pcie3_phy;
/delete-node/ &thermal_zones;
+/delete-node/ &etm8;
+/delete-node/ &etm9;
+/delete-node/ &etm10;
+/delete-node/ &etm11;
+/delete-node/ &cluster2_funnel_l1;
+/delete-node/ &cluster2_funnel_l2;
+/delete-node/ &cluster2_etf;
+/delete-node/ &cluster2_rep_2_0;
+/delete-node/ &cluster2_rep_2_1;
+/delete-node/ &cluster2_rep_2_2;
+/delete-node/ &cluster2_rep_2_3;
+/delete-node/ &apss_funnel_in2;
&gcc {
compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
--
2.34.1
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