Message-ID: <20251028073534.526992-1-richard.genoud@bootlin.com>
Date: Tue, 28 Oct 2025 08:34:53 +0100
From: Richard Genoud <richard.genoud@...tlin.com>
To: Miquel Raynal <miquel.raynal@...tlin.com>,
	Richard Weinberger <richard@....at>,
	Vignesh Raghavendra <vigneshr@...com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Chen-Yu Tsai <wens@...e.org>,
	Jernej Skrabec <jernej.skrabec@...il.com>,
	Samuel Holland <samuel@...lland.org>
Cc: Uwe Kleine-König <u.kleine-koenig@...libre.com>,
	Wentao Liang <vulab@...as.ac.cn>,
	Johan Hovold <johan@...nel.org>,
	Maxime Ripard <mripard@...nel.org>,
	Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
	linux-mtd@...ts.infradead.org,
	devicetree@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-sunxi@...ts.linux.dev,
	linux-kernel@...r.kernel.org,
	Richard Genoud <richard.genoud@...tlin.com>
Subject: [PATCH v4 00/16] Introduce Allwinner H6/H616 NAND controller support

Hi everyone,

This patch series introduce H6/H616 NAND controller support (but not yet
the DMA/MDMA part).

All the work was done on a H616 board with a Kioxia TC58NVG1S3HTA00 NAND
chip.
ECC is supported, as well as scrambling.

H6 SoC has not been tested, but it shares all registers with H616, plus
some registers dedicated to Embedded Crypto Engine that H616 lacks.

This IP has quite some register fields modified from the A10/A23, but in
the end, it works more or less the same.
Main differences with A10/A23 are:
- The need for 2 more clocks (for ECC and MBUS)
- The use of a new USER_DATA_LEN register
- More ECC strengths (44, 52, 68, 72, 76 and 80 bits / 1KB)
- MDMA based on chained buffers
- some registers layouts have changed (mainly due do the stronger ECC)

Patch 1 introduces allwinner,sun50i-h616-nand-controller compatible
in order to differentiate from the A10 and A23.

Patch 2 removes a superfluous call, and is independent from the others.

Patch 3 replaces the hard coded value '4' used for user data length by
a more meaningful define

Patches 4-14 are paving the way to the introduction of H616 NAND
controller support.
They are small, without functional change and easier to review than a
big patch.
They move a fixed value (register offset, field mask, SRAM size) into
the struct sunxi_nfc_caps when this value is different on H6/H616.

Patch 15 introduces the support for H6/H616 NAND controller.

Patch 16 adds the NAND controller node to sun50i-h616.dtsi

Changes from v3:
- fix patches order by beginning with binding patch and finishing with
  dts patch
- add a patch to replace user data length hard coded value by a define
  as suggested by Miquèl
- un-break a line in patch 5 as suggested by Miquèl
- update Geert's series link to v5
- update patch 8 commit message with a mention to Geert's series
- address Miquèl remarks on patch 15:
  - change // to /* */
  - remove statics set to false

Changes from v2:
- add missing 'status = "disabled";' in nand controller node.
- factorize back clock/clock-names in binding.
- pick-up reviewed-by

Changes from v1:
- reorder patches to have dtsi/bindings patches at the end.
- reorder nand-controller and pins nodes to respect the order.
- add /omit-if-no-ref/ on pins that may be unused.
- remove pinctrl from nand controller node (this should be added to device
 DT).
- rework dt binding.
- fix H616 comment on chained descriptors support.
- add missing mbus_clk description.
- make ECC clock mandatory for H6 (because it's indeed mandatory).
- harmonize new clock retrieving error messages with older ones.
- harmonize commits subjects (mtd: rawnand: sunxi).
- reword commit messages to use imperative mood.
- pick-up reviewed-by

Thanks Krzysztof, Jernej, Chen-Yu and Miquèl for the reviews!

Regards,
Richard

Richard Genoud (16):
  dt-bindings: mtd: sunxi: Add H616 compatible
  mtd: rawnand: sunxi: Remove superfluous register readings
  mtd: rawnand: sunxi: Replace hard coded value by a define
  mtd: rawnand: sunxi: move ECC strenghts in sunxi_nfc_caps
  mtd: rawnand: sunxi: introduce reg_ecc_err_cnt in sunxi_nfc_caps
  mtd: rawnand: sunxi: introduce reg_user_data in sunxi_nfc_caps
  mtd: rawnand: sunxi: rework pattern found registers
  mtd: rawnand: sunxi: add has_ecc_block_512 capability
  mtd: rawnand: sunxi: introduce ecc_mode_mask in sunxi_nfc_caps
  mtd: rawnand: sunxi: introduce random en/dir in sunxi_nfc_caps
  mtd: rawnand: sunxi: introduce reg_pat_id in sunxi_nfc_caps
  mtd: rawnand: sunxi: introduce reg_spare_area in sunxi_nfc_caps
  mtd: rawnand: sunxi: introduce ecc_err_mask in sunxi_nfc_caps
  mtd: rawnand: sunxi: introduce sram_size in sunxi_nfc_caps
  mtd: rawnand: sunxi: Add support for H616 nand controller
  arm64: dts: allwinner: h616: add NAND controller

 .../mtd/allwinner,sun4i-a10-nand.yaml         |  41 +-
 .../arm64/boot/dts/allwinner/sun50i-h616.dtsi |  52 +++
 drivers/mtd/nand/raw/sunxi_nand.c             | 407 +++++++++++++++---
 3 files changed, 426 insertions(+), 74 deletions(-)


base-commit: 3a8660878839faadb4f1a6dd72c3179c1df56787
-- 
2.47.3

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