linux-kernel - [PATCH 3/6] EDAC/altera: Add DBE interrupt handling for Agilex5

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Message-Id: <20251028092232.773991-4-niravkumarlaxmidas.rabara@altera.com>
Date: Tue, 28 Oct 2025 17:22:29 +0800
From: niravkumarlaxmidas.rabara@...era.com
To: dinguyen@...nel.org,
	matthew.gerlach@...era.com,
	robh@...nel.org,
	krzk+dt@...nel.org,
	conor+dt@...nel.org,
	bp@...en8.de,
	tony.luck@...el.com
Cc: linux-edac@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Niravkumar L Rabara <niravkumarlaxmidas.rabara@...era.com>
Subject: [PATCH 3/6] EDAC/altera: Add DBE interrupt handling for Agilex5

From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@...era.com>

Agilex5 SoCFPGA uses a dedicated interrupt for Double Bit Error (DBE)
reporting, unlike other 64-bit SoCFPGA platforms (Agilex7 and Stratix10)
which signal DBE events via Asynchronous SError interrupts.

Add Agilex5-specific handling to differentiate between these platforms and
correctly process DBE interrupt.

Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@...era.com>
---
 drivers/edac/altera_edac.c | 42 ++++++++++++++++++++++++++++++++------
 1 file changed, 36 insertions(+), 6 deletions(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 103b2c2eba2a..ee3270bf75e6 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1966,12 +1966,32 @@ static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
 	}
 
 #ifdef CONFIG_64BIT
-	/* Use IRQ to determine SError origin instead of assigning IRQ */
-	rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq);
-	if (rc) {
-		edac_printk(KERN_ERR, EDAC_DEVICE,
-			    "Unable to parse DB IRQ index\n");
-		goto err_release_group1;
+	if (of_machine_is_compatible("intel,socfpga-agilex5")) {
+		altdev->db_irq = irq_of_parse_and_map(np, 1);
+		if (!altdev->db_irq) {
+			edac_printk(KERN_ERR, EDAC_DEVICE,
+				    "Error allocating DBIRQ\n");
+			rc = -ENODEV;
+			goto err_release_group1;
+		}
+		rc = devm_request_irq(edac->dev, altdev->db_irq,
+				      prv->ecc_irq_handler,
+				      IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
+				      ecc_name, altdev);
+		if (rc) {
+			edac_printk(KERN_ERR, EDAC_DEVICE,
+				    "No DBERR IRQ resource\n");
+			goto err_release_group1;
+		}
+	} else {
+		/* Use IRQ to determine SError origin instead of assigning IRQ */
+		rc = of_property_read_u32_index(np, "interrupts", 0,
+						&altdev->db_irq);
+		if (rc) {
+			edac_printk(KERN_ERR, EDAC_DEVICE,
+				    "Unable to parse DB IRQ index\n");
+			goto err_release_group1;
+		}
 	}
 #else
 	altdev->db_irq = irq_of_parse_and_map(np, 1);
@@ -2145,6 +2165,16 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
 					 altr_edac_a10_irq_handler,
 					 edac);
 
+	if (of_machine_is_compatible("intel,socfpga-agilex5")) {
+		edac->db_irq = platform_get_irq_byname(pdev, "global_dbe");
+		if (edac->db_irq < 0)
+			return edac->db_irq;
+
+		irq_set_chained_handler_and_data(edac->db_irq,
+						 altr_edac_a10_irq_handler,
+						 edac);
+	}
+
 #ifdef CONFIG_64BIT
 	{
 		int dberror, err_addr;
-- 
2.25.1