linux-kernel - [PATCH 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region

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Message-ID: <a3182556c07839dcd9227fa6a4a9d295507f3e8e.1761643239.git.khairul.anuar.romli@altera.com>
Date: Tue, 28 Oct 2025 17:29:00 +0800
From: Khairul Anuar Romli <khairul.anuar.romli@...era.com>
To: Dinh Nguyen <dinguyen@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Mahesh Rao <mahesh.rao@...era.com>,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org (open list),
	Khairul Anuar Romli <khairul.anuar.romli@...era.com>
Subject: [PATCH 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region

Introduce the Stratix10 SoC service layer (SVC) node for Agilex5 SoCs.
The node includes the compatible string "intel,agilex5-svc" and references
a reserved memory region required for communication with the Secure Device
Manager (SDM).

Agilex5 introduces a dependency on IOMMU-based translation for reserved
memory, unlike prior Agilex platforms. This commit introduces the
structural changes needed to support this feature once the IOMMU driver
is upstreamed.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@...era.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index a13ccee3c4c3..15284092897e 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -841,5 +841,14 @@ queue7 {
 				};
 			};
 		};
+
+		firmware {
+			svc {
+				compatible = "intel,agilex5-svc";
+				method = "smc";
+				memory-region = <&service_reserved>;
+				iommus = <&smmu 10>;
+			};
+		};
 	};
 };
-- 
2.43.7