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Message-ID: <20251029144336.356816-1-srinivas.kandagatla@oss.qualcomm.com>
Date: Wed, 29 Oct 2025 14:43:35 +0000
From: Srinivas Kandagatla <srinivas.kandagatla@....qualcomm.com>
To: broonie@...nel.org
Cc: perex@...ex.cz, tiwai@...e.com, srini@...nel.org,
        linux-sound@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, konrad.dybcio@....qualcomm.com,
        prasad.kumpatla@....qualcomm.com,
        Srinivas Kandagatla <srinivas.kandagatla@....qualcomm.com>
Subject: [PATCH] ASoC: codecs: va-macro: fix revision checking
The revision rework patch seems to have reversed the bit positions for
macro presence in core_id_1 register.
This broken RB1 and Arduino UnoQ audio.
Fix these bit positions to correctly reflect the register definition.
Fixes: 281c97376cfc ("ASoC: codecs: va-macro: Rework version checking")
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@....qualcomm.com>
---
 sound/soc/codecs/lpass-va-macro.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/sound/soc/codecs/lpass-va-macro.c b/sound/soc/codecs/lpass-va-macro.c
index 2b0ecc52c6be..fbe5ebeeaa80 100644
--- a/sound/soc/codecs/lpass-va-macro.c
+++ b/sound/soc/codecs/lpass-va-macro.c
@@ -67,10 +67,10 @@
 #define CDC_VA_TOP_CSR_CORE_ID_0		(0x00C0)
  #define CORE_ID_0_REV_MAJ			GENMASK(7, 0)
 #define CDC_VA_TOP_CSR_CORE_ID_1		(0x00C4)
-#define CORE_ID_1_HAS_WSAMACRO			BIT(3)
-#define CORE_ID_1_HAS_RXMACRO			BIT(2)
-#define CORE_ID_1_HAS_TXMACRO			BIT(1)
-#define CORE_ID_1_HAS_VAMACRO			BIT(0)
+#define CORE_ID_1_HAS_WSAMACRO			BIT(0)
+#define CORE_ID_1_HAS_RXMACRO			BIT(1)
+#define CORE_ID_1_HAS_TXMACRO			BIT(2)
+#define CORE_ID_1_HAS_VAMACRO			BIT(3)
 #define CDC_VA_TOP_CSR_CORE_ID_2		(0x00C8)
  #define CORE_ID_2_REV_MIN			GENMASK(7, 4)
  #define CORE_ID_2_REV_STEP			GENMASK(3, 0)
-- 
2.51.0
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