linux-kernel - Re: [PATCH v7 2/8] x86/mce: Unify AMD DFR handler with MCA Polling

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Message-ID: <20251029150912.GA113329@yaz-khff2.amd.com>
Date: Wed, 29 Oct 2025 11:09:12 -0400
From: Yazen Ghannam <yazen.ghannam@....com>
To: Borislav Petkov <bp@...en8.de>
Cc: x86@...nel.org, Tony Luck <tony.luck@...el.com>,
	"Rafael J. Wysocki" <rafael@...nel.org>,
	Len Brown <lenb@...nel.org>, linux-kernel@...r.kernel.org,
	linux-edac@...r.kernel.org, Smita.KoralahalliChannabasappa@....com,
	Qiuxu Zhuo <qiuxu.zhuo@...el.com>,
	Nikolay Borisov <nik.borisov@...e.com>,
	Bert Karwatzki <spasswolf@....de>, linux-acpi@...r.kernel.org
Subject: Re: [PATCH v7 2/8] x86/mce: Unify AMD DFR handler with MCA Polling

On Wed, Oct 29, 2025 at 12:18:25AM +0100, Borislav Petkov wrote:
> On Tue, Oct 28, 2025 at 04:37:19PM -0400, Yazen Ghannam wrote:
> > Yep, that's it. Much cleaner. :)
> 
> :-)
> 
> Final version:
> 
> From dd705221b2b3fb06fd2dc25dd51a8aaa1b1bd6d5 Mon Sep 17 00:00:00 2001
> From: Yazen Ghannam <yazen.ghannam@....com>
> Date: Thu, 16 Oct 2025 16:37:48 +0000
> Subject: [PATCH] x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA
>  systems
> 

^^^ This is the following patch.
https://lore.kernel.org/all/20251016-wip-mca-updates-v7-3-5c139a4062cb@amd.com/

Why apply the fix ups to that?

Thanks,
Yazen

[...]

> diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
> index 7be062429ce3..4aff14e04287 100644
> --- a/arch/x86/kernel/cpu/mce/core.c
> +++ b/arch/x86/kernel/cpu/mce/core.c
> @@ -726,24 +726,11 @@ DEFINE_PER_CPU(unsigned, mce_poll_count);
>   * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and
>   *    log it.
>   */
> -static bool smca_should_log_poll_error(enum mcp_flags flags, struct mce_hw_err *err)
> +static bool smca_should_log_poll_error(struct mce *m)
>  {
> -	struct mce *m = &err->m;
> -
> -	/*
> -	 * If the MCA_STATUS register has a deferred error, then continue using it as
> -	 * the status register.
> -	 *
> -	 * MCA_DESTAT will be cleared at the end of the handler.
> -	 */
> -	if ((m->status & MCI_STATUS_VAL) && (m->status & MCI_STATUS_DEFERRED))
> +	if (m->status & MCI_STATUS_VAL)
>  		return true;
>  
> -	/*
> -	 * If the MCA_DESTAT register has a deferred error, then use it instead.
> -	 *
> -	 * MCA_STATUS will not be cleared at the end of the handler.
> -	 */
>  	m->status = mce_rdmsrq(MSR_AMD64_SMCA_MCx_DESTAT(m->bank));
>  	if ((m->status & MCI_STATUS_VAL) && (m->status & MCI_STATUS_DEFERRED)) {
>  		m->kflags |= MCE_CHECK_DFR_REGS;
> @@ -780,7 +767,7 @@ static bool should_log_poll_error(enum mcp_flags flags, struct mce_hw_err *err)
>  	struct mce *m = &err->m;
>  
>  	if (mce_flags.smca)
> -		return smca_should_log_poll_error(flags, err);
> +		return smca_should_log_poll_error(m);
>  
>  	/* If this entry is not valid, ignore it. */
>  	if (!(m->status & MCI_STATUS_VAL))
> --