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Message-ID: <20251029-timing-venue-1cd20c3450ac@spud> Date: Wed, 29 Oct 2025 16:11:23 +0000 From: Conor Dooley <conor@...nel.org> To: claudiu.beznea@...on.dev Cc: conor@...nel.org, Conor Dooley <conor.dooley@...rochip.com>, Daire McNamara <daire.mcnamara@...rochip.com>, pierre-henry.moussay@...rochip.com, valentina.fernandezalanis@...rochip.com, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de>, linux-riscv@...ts.infradead.org, linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org Subject: [PATCH v6 7/7] MAINTAINERS: rename Microchip RISC-V entry From: Conor Dooley <conor.dooley@...rochip.com> There's now non-FPGA RISC-V SoCs from Microchip, so rename the entry to reflect that. Signed-off-by: Conor Dooley <conor.dooley@...rochip.com> --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index a28740a7d87a..24efae3df425 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22079,7 +22079,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux.git F: Documentation/devicetree/bindings/iommu/riscv,iommu.yaml F: drivers/iommu/riscv/ -RISC-V MICROCHIP FPGA SUPPORT +RISC-V MICROCHIP SUPPORT M: Conor Dooley <conor.dooley@...rochip.com> M: Daire McNamara <daire.mcnamara@...rochip.com> L: linux-riscv@...ts.infradead.org -- 2.51.0
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