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Message-ID: <u6f4spt62rzqyqifaza7q34e7vf2jmbrbmzmgxtlhjupya3lsy@6vvssqcfhmtg>
Date: Wed, 29 Oct 2025 11:43:04 -0500
From: Bjorn Andersson <andersson@...nel.org>
To: Abel Vesa <abel.vesa@...aro.org>
Cc: Vinod Koul <vkoul@...nel.org>, 
	Kishon Vijay Abraham I <kishon@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Dmitry Baryshkov <lumag@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>, 
	Sibi Sankar <sibi.sankar@....qualcomm.com>, Rajendra Nayak <quic_rjendra@...cinc.com>, 
	Neil Armstrong <neil.armstrong@...aro.org>, linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Krzysztof Kozlowski <krzk@...nel.org>, stable@...r.kernel.org
Subject: Re: [PATCH v4 3/3] arm64: dts: qcom: x1e80100: Add missing TCSR ref
 clock to the DP PHYs

On Wed, Oct 29, 2025 at 03:31:32PM +0200, Abel Vesa wrote:
> The DP PHYs on X1E80100 need the ref clock which is provided by the
> TCSR CC.
> 
> The current X Elite devices supported upstream work fine without this
> clock, because the boot firmware leaves this clock enabled. But we should
> not rely on that. Also, even though this change breaks the ABI, it is
> needed in order to make the driver disables this clock along with the
> other ones, for a proper bring-down of the entire PHY.
> 
> So lets attach it to each of the DP PHYs in order to do that.
> 
> Cc: stable@...r.kernel.org # v6.9
> Fixes: 1940c25eaa63 ("arm64: dts: qcom: x1e80100: Add display nodes")

Reviewed-by: Bjorn Andersson <andersson@...nel.org>

> Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> ---
>  arch/arm64/boot/dts/qcom/hamoa.dtsi | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> index a17900eacb20396a9792efcfcd6ce6dd877435d1..59603616a3c229c69467c41e6043c63daa62b46b 100644
> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> @@ -5896,9 +5896,11 @@ mdss_dp2_phy: phy@...2a00 {
>  			      <0 0x0aec2000 0 0x1c8>;
>  
>  			clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
> -				 <&dispcc DISP_CC_MDSS_AHB_CLK>;
> +				 <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +				 <&tcsr TCSR_EDP_CLKREF_EN>;
>  			clock-names = "aux",
> -				      "cfg_ahb";
> +				      "cfg_ahb",
> +				      "ref";
>  
>  			power-domains = <&rpmhpd RPMHPD_MX>;
>  
> @@ -5916,9 +5918,11 @@ mdss_dp3_phy: phy@...5a00 {
>  			      <0 0x0aec5000 0 0x1c8>;
>  
>  			clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
> -				 <&dispcc DISP_CC_MDSS_AHB_CLK>;
> +				 <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +				 <&tcsr TCSR_EDP_CLKREF_EN>;
>  			clock-names = "aux",
> -				      "cfg_ahb";
> +				      "cfg_ahb",
> +				      "ref";
>  
>  			power-domains = <&rpmhpd RPMHPD_MX>;
>  
> 
> -- 
> 2.48.1
> 

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