linux-kernel - Re: [patch V3 03/20] sched/mmcid: Cacheline align MM CID storage

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Message-ID: <87y0ottny9.ffs@tglx>
Date: Wed, 29 Oct 2025 22:09:18 +0100
From: Thomas Gleixner <tglx@...utronix.de>
To: Mathieu Desnoyers <mathieu.desnoyers@...icios.com>, LKML
 <linux-kernel@...r.kernel.org>
Cc: Peter Zijlstra <peterz@...radead.org>, Gabriele Monaco
 <gmonaco@...hat.com>, Michael Jeanson <mjeanson@...icios.com>, Jens Axboe
 <axboe@...nel.dk>, "Paul E. McKenney" <paulmck@...nel.org>, "Gautham R.
 Shenoy" <gautham.shenoy@....com>, Florian Weimer <fweimer@...hat.com>, Tim
 Chen <tim.c.chen@...el.com>, Yury Norov <yury.norov@...il.com>, Shrikanth
 Hegde <sshegde@...ux.ibm.com>
Subject: Re: [patch V3 03/20] sched/mmcid: Cacheline align MM CID storage

On Wed, Oct 29 2025 at 11:39, Mathieu Desnoyers wrote:
> On 2025-10-29 09:08, Thomas Gleixner wrote:
> [...]
>>   struct mm_cid_pcpu {
>>   	unsigned int	cid;
>> -};
>> +}____cacheline_aligned_in_smp;
>
> What's the point in cacheline aligning this per-CPU variable ?
> Should we expect other accesses to per-CPU variables sharing the
> same cache line to update them frequently from remote CPUs ?
>
> I did not cacheline align it expecting that per-CPU variables are
> typically updated from their respective CPUs. So perhaps reality
> don't match my expectations, but that's news to me.

It depends. While per CPU variables are typically updated only on the
local CPU there are situations where there is cross CPU access and it
really depends in which proximity it ends up. I made it that way because
I saw the accesses prominent in perf top, which means there is
contention on the cache line.

Thanks,

        tglx