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Message-Id: <20251029-automatic-clocks-v2-4-f8edd3a2d82b@linaro.org>
Date: Wed, 29 Oct 2025 21:29:25 +0000
From: Peter Griffin <peter.griffin@...aro.org>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Alim Akhtar <alim.akhtar@...sung.com>,
André Draszik <andre.draszik@...aro.org>,
Tudor Ambarus <tudor.ambarus@...aro.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Sam Protsenko <semen.protsenko@...aro.org>,
Sylwester Nawrocki <s.nawrocki@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>
Cc: Will McVicker <willmcvicker@...gle.com>,
Krzysztof Kozlowski <krzk@...nel.org>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
kernel-team@...roid.com, Peter Griffin <peter.griffin@...aro.org>,
Krzysztof Kozlowski <krzk@...nel.org>
Subject: [PATCH v2 4/4] clk: samsung: gs101: Enable auto_clock_gate mode
for each gs101 CMU
Enable auto clock mode, and define the additional fields which are used
when this mode is enabled.
/sys/kernel/debug/clk/clk_summary now reports approximately 308 running
clocks and 298 disabled clocks. Prior to this commit 586 clocks were
running and 17 disabled.
Signed-off-by: Peter Griffin <peter.griffin@...aro.org>
---
drivers/clk/samsung/clk-gs101.c | 56 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
index 70b26db9b95ad0b376d23f637c7683fbc8c8c600..68c5ed8f0fe1cac5169313b6ec705f9eec44ff53 100644
--- a/drivers/clk/samsung/clk-gs101.c
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -9,6 +9,7 @@
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/google,gs101.h>
@@ -26,6 +27,10 @@
#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
+#define GS101_GATE_DBG_OFFSET 0x4000
+#define GS101_DRCG_EN_OFFSET 0x104
+#define GS101_MEMCLK_OFFSET 0x108
+
/* ---- CMU_TOP ------------------------------------------------------------- */
/* Register Offset definitions for CMU_TOP (0x1e080000) */
@@ -1433,6 +1438,9 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
.nr_clk_ids = CLKS_NR_TOP,
.clk_regs = cmu_top_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cmu_top_clk_regs),
+ .auto_clock_gate = true,
+ .gate_dbg_offset = GS101_GATE_DBG_OFFSET,
+ .option_offset = CMU_CMU_TOP_CONTROLLER_OPTION,
};
static void __init gs101_cmu_top_init(struct device_node *np)
@@ -1900,6 +1908,11 @@ static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0),
};
+static const unsigned long dcrg_memclk_sysreg[] __initconst = {
+ GS101_DRCG_EN_OFFSET,
+ GS101_MEMCLK_OFFSET,
+};
+
static const struct samsung_cmu_info apm_cmu_info __initconst = {
.mux_clks = apm_mux_clks,
.nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
@@ -1912,6 +1925,12 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
.nr_clk_ids = CLKS_NR_APM,
.clk_regs = apm_clk_regs,
.nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
+ .sysreg_clk_regs = dcrg_memclk_sysreg,
+ .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg),
+ .auto_clock_gate = true,
+ .gate_dbg_offset = GS101_GATE_DBG_OFFSET,
+ .drcg_offset = GS101_DRCG_EN_OFFSET,
+ .memclk_offset = GS101_MEMCLK_OFFSET,
};
/* ---- CMU_HSI0 ------------------------------------------------------------ */
@@ -2375,7 +2394,14 @@ static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
.nr_clk_ids = CLKS_NR_HSI0,
.clk_regs = hsi0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs),
+ .sysreg_clk_regs = dcrg_memclk_sysreg,
+ .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg),
.clk_name = "bus",
+ .auto_clock_gate = true,
+ .gate_dbg_offset = GS101_GATE_DBG_OFFSET,
+ .option_offset = HSI0_CMU_HSI0_CONTROLLER_OPTION,
+ .drcg_offset = GS101_DRCG_EN_OFFSET,
+ .memclk_offset = GS101_MEMCLK_OFFSET,
};
/* ---- CMU_HSI2 ------------------------------------------------------------ */
@@ -2863,7 +2889,14 @@ static const struct samsung_cmu_info hsi2_cmu_info __initconst = {
.nr_clk_ids = CLKS_NR_HSI2,
.clk_regs = cmu_hsi2_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cmu_hsi2_clk_regs),
+ .sysreg_clk_regs = dcrg_memclk_sysreg,
+ .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg),
.clk_name = "bus",
+ .auto_clock_gate = true,
+ .gate_dbg_offset = GS101_GATE_DBG_OFFSET,
+ .option_offset = HSI2_CMU_HSI2_CONTROLLER_OPTION,
+ .drcg_offset = GS101_DRCG_EN_OFFSET,
+ .memclk_offset = GS101_MEMCLK_OFFSET,
};
/* ---- CMU_MISC ------------------------------------------------------------ */
@@ -3423,7 +3456,14 @@ static const struct samsung_cmu_info misc_cmu_info __initconst = {
.nr_clk_ids = CLKS_NR_MISC,
.clk_regs = misc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(misc_clk_regs),
+ .sysreg_clk_regs = dcrg_memclk_sysreg,
+ .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg),
.clk_name = "bus",
+ .auto_clock_gate = true,
+ .gate_dbg_offset = GS101_GATE_DBG_OFFSET,
+ .option_offset = MISC_CMU_MISC_CONTROLLER_OPTION,
+ .drcg_offset = GS101_DRCG_EN_OFFSET,
+ .memclk_offset = GS101_MEMCLK_OFFSET,
};
static void __init gs101_cmu_misc_init(struct device_node *np)
@@ -4010,6 +4050,10 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
21, 0, 0),
};
+static const unsigned long dcrg_sysreg[] __initconst = {
+ GS101_DRCG_EN_OFFSET,
+};
+
static const struct samsung_cmu_info peric0_cmu_info __initconst = {
.mux_clks = peric0_mux_clks,
.nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
@@ -4020,7 +4064,13 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
.nr_clk_ids = CLKS_NR_PERIC0,
.clk_regs = peric0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
+ .sysreg_clk_regs = dcrg_sysreg,
+ .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_sysreg),
.clk_name = "bus",
+ .auto_clock_gate = true,
+ .gate_dbg_offset = GS101_GATE_DBG_OFFSET,
+ .option_offset = PERIC0_CMU_PERIC0_CONTROLLER_OPTION,
+ .drcg_offset = GS101_DRCG_EN_OFFSET,
};
/* ---- CMU_PERIC1 ---------------------------------------------------------- */
@@ -4368,7 +4418,13 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = {
.nr_clk_ids = CLKS_NR_PERIC1,
.clk_regs = peric1_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
+ .sysreg_clk_regs = dcrg_sysreg,
+ .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_sysreg),
.clk_name = "bus",
+ .auto_clock_gate = true,
+ .gate_dbg_offset = GS101_GATE_DBG_OFFSET,
+ .option_offset = PERIC1_CMU_PERIC1_CONTROLLER_OPTION,
+ .drcg_offset = GS101_DRCG_EN_OFFSET,
};
/* ---- platform_driver ----------------------------------------------------- */
--
2.51.1.851.g4ebd6896fd-goog
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