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Message-ID: <176173058644.2601451.4553554490915980838.tip-bot2@tip-bot2>
Date: Wed, 29 Oct 2025 09:36:26 -0000
From: "tip-bot2 for Zide Chen" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Zhenyu Wang <zhenyuw.linux@...il.com>, Zide Chen <zide.chen@...el.com>,
 "Peter Zijlstra (Intel)" <peterz@...radead.org>,
 Kan Liang <kan.liang@...ux.intel.com>, Dapeng Mi <dapeng1.mi@...ux.intel.com>,
 x86@...nel.org, linux-kernel@...r.kernel.org
Subject: [tip: perf/core] perf/x86/intel/cstate: Add Clearwater Forest support
The following commit has been merged into the perf/core branch of tip:
Commit-ID:     e39b82f6cb0526c551d4651ba6d286b6b1f9e9c3
Gitweb:        https://git.kernel.org/tip/e39b82f6cb0526c551d4651ba6d286b6b1f9e9c3
Author:        Zide Chen <zide.chen@...el.com>
AuthorDate:    Thu, 23 Oct 2025 15:37:51 -07:00
Committer:     Peter Zijlstra <peterz@...radead.org>
CommitterDate: Wed, 29 Oct 2025 10:29:53 +01:00
perf/x86/intel/cstate: Add Clearwater Forest support
Clearwater Forest is based on the Darkmont Atom microarchitecture.
>>From the perspective of C-state residency profiling, it supports the
same residency counters as Sierra Forest: CC1/CC6, PC2/PC6, and MC6.
Please note that the C1E residency counter can only be read via PMT,
not MSR. Therefore, tools relying on the perf_event framework cannot
access the C1E residency.
Signed-off-by: Zhenyu Wang <zhenyuw.linux@...il.com>
Signed-off-by: Zide Chen <zide.chen@...el.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Reviewed-by: Kan Liang <kan.liang@...ux.intel.com>
Reviewed-by: Dapeng Mi <dapeng1.mi@...ux.intel.com>
Link: https://patch.msgid.link/20251023223754.1743928-2-zide.chen@intel.com
---
 arch/x86/events/intel/cstate.c | 1 +
 1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index ec753e3..a5f2e0b 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -628,6 +628,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 	X86_MATCH_VFM(INTEL_ATOM_GRACEMONT,	&adl_cstates),
 	X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X,	&srf_cstates),
 	X86_MATCH_VFM(INTEL_ATOM_CRESTMONT,	&grr_cstates),
+	X86_MATCH_VFM(INTEL_ATOM_DARKMONT_X,	&srf_cstates),
 
 	X86_MATCH_VFM(INTEL_ICELAKE_L,		&icl_cstates),
 	X86_MATCH_VFM(INTEL_ICELAKE,		&icl_cstates),
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