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Message-ID: <e9e117ed-823c-47e3-8ed6-14dbecc844bc@linaro.org>
Date: Wed, 29 Oct 2025 11:25:50 +0100
From: Neil Armstrong <neil.armstrong@...aro.org>
To: Jens Reidel <adrian@...nlining.org>,
Rob Clark <robin.clark@....qualcomm.com>, Sean Paul <sean@...rly.run>,
Konrad Dybcio <konradybcio@...nel.org>, Dmitry Baryshkov <lumag@...nel.org>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Jessica Zhang <jessica.zhang@....qualcomm.com>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH RFC RFT] drm/msm: adreno: attach the GMU device to a
driver
Hi,
On 10/26/25 02:31, Jens Reidel wrote:
> On 10/22/25 14:44, Neil Armstrong wrote:
>> Due to the sync_state is enabled by default in pmdomain & CCF since v6.17,
>> the GCC and GPUCC sync_state would stay pending, leaving the resources in
>> full performance:
>> gcc-x1e80100 100000.clock-controller: sync_state() pending due to 3d6a000.gmu
>> gpucc-x1e80100 3d90000.clock-controller: sync_state() pending due to 3d6a000.gmu
>>
>> In order to fix this state and allow the GMU to be properly
>> probed, let's add a proper driver for the GMU and add it to
>> the MSM driver components.
>>
>> Only the proper GMU has been tested since I don't have
>> access to hardware with a GMU wrapper.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
>> ---
>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 354 ++++++++++++++---------------
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 -
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 3 -
>> drivers/gpu/drm/msm/adreno/adreno_device.c | 4 +
>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 4 +
>> drivers/gpu/drm/msm/msm_drv.c | 16 +-
>> 6 files changed, 192 insertions(+), 195 deletions(-)
>>
<snip>
>>
>> ---
>> base-commit: 211ddde0823f1442e4ad052a2f30f050145ccada
>> change-id: 20251022-topic-adreno-attach-gmu-to-driver-e47025fd7ebb
>>
>> Best regards,
>
> Hi Neil,
>
> thanks for the patch. With it applied, my GPU fails to initialize.
> Here's the related dmesg section:
>
> [ 1.733062] [drm:dpu_kms_hw_init:1173] dpu hardware revision:0x50020000
> [ 1.735229] [drm] Initialized msm 1.13.0 for ae01000.display-controller on minor 0
> [ 1.735403] msm_dpu ae01000.display-controller: [drm:adreno_request_fw] loaded qcom/a630_sqe.fw from new location
> [ 1.735513] msm_dpu ae01000.display-controller: [drm:adreno_request_fw] loaded qcom/a630_gmu.bin from new location
> [ 1.746710] a6xx_gmu 506a000.gmu: [drm:a6xx_gmu_set_oob] *ERROR* Timeout waiting for GMU OOB set BOOT_SLUMBER: 0x800000
> [ 1.746766] msm_dpu ae01000.display-controller: [drm:adreno_load_gpu] *ERROR* Couldn't power up the GPU: -110
>
> This could be because I have an Adreno 630-family GPU, which is marked as legacy in a6xx_gmu_init / a6xx_gmu_bind. Previously, the rest of the init code would just always run, while now, some parts are conditionally disabled for legacy GPUs - that may be unintentional? However, unconditionally enabling those parts seems to fail to initialize the GPU followed by a reset shortly after, so there's probably more to this.
>
> Please let me know if there's anything I can do to help debug this.
Thanks for the report, it's an sdm845 based right ?
I may have mismatched the role of the legacy parameter...
Could you try this on top:
===========================><=====================================
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 6e7c3e627509..403675ed18c7 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -1925,6 +1925,7 @@ static int a6xx_gmu_bind(struct device *dev, struct device *master, void *data)
struct msm_drm_private *priv = dev_get_drvdata(master);
struct msm_gpu *gpu = dev_to_gpu(&priv->gpu_pdev->dev);
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+ bool is_wrapper = adreno_has_gmu_wrapper(adreno_gpu);
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
struct device_link *link;
@@ -1936,18 +1937,18 @@ static int a6xx_gmu_bind(struct device *dev, struct device *master, void *data)
if (ret)
return ret;
- if (adreno_has_gmu_wrapper(adreno_gpu))
+ if (is_wrapper)
/* Mark legacy for manual SPTPRAC control */
gmu->legacy = true;
- if (!gmu->legacy)
+ if (!is_wrapper)
/* Set GMU idle level */
gmu->idle_level = (adreno_gpu->info->quirks & ADRENO_QUIRK_IFPC) ?
GMU_IDLE_STATE_IFPC : GMU_IDLE_STATE_ACTIVE;
pm_runtime_enable(gmu->dev);
- if (!gmu->legacy) {
+ if (!is_wrapper) {
/* Get the list of clocks */
ret = a6xx_gmu_clocks_probe(gmu);
if (ret)
@@ -2063,7 +2064,7 @@ static int a6xx_gmu_bind(struct device *dev, struct device *master, void *data)
goto detach_cxpd;
}
- if (!gmu->legacy) {
+ if (!is_wrapper) {
/* Other errors are handled during GPU ACD probe */
gmu->qmp = qmp_get(gmu->dev);
if (PTR_ERR_OR_ZERO(gmu->qmp) == -EPROBE_DEFER) {
@@ -2082,7 +2083,7 @@ static int a6xx_gmu_bind(struct device *dev, struct device *master, void *data)
*/
gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
- if (!gmu->legacy) {
+ if (!is_wrapper) {
/* Get the power levels for the GMU and GPU */
a6xx_gmu_pwrlevels_probe(gmu);
@@ -2115,7 +2116,7 @@ static int a6xx_gmu_bind(struct device *dev, struct device *master, void *data)
err_mmio:
iounmap(gmu->mmio);
- if (!gmu->legacy) {
+ if (!is_wrapper) {
if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
iounmap(gmu->rscc);
free_irq(gmu->gmu_irq, gmu);
@@ -2123,7 +2124,7 @@ static int a6xx_gmu_bind(struct device *dev, struct device *master, void *data)
}
err_memory:
- if (!gmu->legacy)
+ if (!is_wrapper)
a6xx_gmu_memory_free(gmu);
return ret;
===========================><=====================================
Thanks,
Neil
>
> Best regards,
> Jens
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